"Class" - The Classical feature - Part I

Dear Readers,

Let's understand the classical feature of System Verilog 'Class'. Here I would try to explain on class feature, object properties and methods, object instantiation, class methods polymorphism and constructor concept.

What is class and why is it classical :), Lets understand
  • Class is a generalization of the data type concept and central to the Object Oriented Programming. 
  • A class is a type that includes data and subroutines like functions and tasks. 
  • The class properties and methods creates a capabilities of some kind of objects.
Usage of class with example:

class AsicWithAnkit ;
//Data of class properties
     bit [3:0] cmd ;
     bit [7:0] addr;
     int count;
     bit ack;

     function new ();
          cmd = 3'b000;
          addr = 8'h00;

     function display ();
         $display ("Command =%h", cmd );
         $display ("Addresss =%h," addr); 
     endfunction : display

     task clean ();
          cmd = 'h0;
          addr = 'h0;
     endtask : clean

endclass : AsicWithAnkit

Above example gives an idea on how to declare a class and their properties, usage of those properties by instantiating class object is the next step to use properties defined inside class body.

Lets understand how to instantiate class object, we will have to create a memory for class object to use class properties and their methods for further development work.

AsicWithAnkit   AwA;
AwA = new ;

Here we can see class name "AsicWithAnkit" is instantiated with a created ovject name "AwA". in second statement we are creating a memory for class object "AwA". Now we are ready to use class properties using instantiated object. Let's understand how?

Now when you want to access or use the properties described in the class you can use/access those methods using the objects.

AsicWithAnkit   AwA = new ;
AwA.cmd = 'h2 ;
AwA.addr = 'h8 ;  //Accessing a class properties using object
AwA.display ();  //Accessing a class method using object

This way we can access class variables and methods using instantiated objects.  System verilog does not require memory allocation and deallocation.

System verilog gives us a different option/way through which we can assign, re-name and copy the objects.
Class has many system verilog features and will try to cover those feature in separate follow up blog posts.

Note : Same blog has been published on EDACafe and is available from here

Keep Reading....
ASIC With Ankit


Unknown said...

Thanks Ankit. good post. Will be waiting for remaining parts too :)

noname said...

Thank you for this superb article.
This is really helpful for someone like me...New in system verilog.

Looking forward to see more articles from you.
Keep it up.

Ankit Gopani said...

Thanks Avinash for reading the following the post, keep reading !!

-ASIC With Ankit

Cliff Cummings said...

Important guideline - one should never use tasks as class methods unless the method consumes simulation time (should be corrected in this post and the next). Using tasks requires that all extended methods must call the base-method task using another task. This means that functions that return values can never call a task-method.

Ankit Gopani said...

Hi Cliff,

Thanks for reading the post and sharing the guidelines. Agree, its recommended to use function if there is no time consuming activity else shall use tasks. One has to be clear about the difference between tasks and functions that I posted in one of my old post. (http://asicwithankit.blogspot.com/2013/01/system-verilog-ignoring-functions.html).

Thanks for pointing this sharing the guidelines.