Class - The Classic Feature - Part II

Dear AWA Readers

Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test bench development.  The usage of class is depends on the requirements.  Let’s understand what different types of classes that we use in system verilog.

Different types of classes:
  1. Basic Class
  2. Abstract Class
  3. Parameterised Class
  4. Nested Class
  5. Typedef Class

Basic Class:
Basic class is covered in my last post, you can refer It from here.

Abstract Class:

Classes without intending to create any objects of class are called Abstract classes.  These type of classes exists simply as a base class from which other classes can be derived. Virtual class is a temple or place holder for derived classes, abstract class is declared with a key word virtual

virtual class asic_with_ankit ;
virtual task awa1 ();
virtual task awa2 ();

Methods (tasks/functions) can be declared virtual, if methods are declared as virtual and is overwritten in derived class, return types, numbers and types of its arguments must be same as of virtual method. Virtual method defined in abstract class need not have body, In this case body will have to be defined in non virtual (non abstract) derived class.

Parameterised class

You might be knowing the parameterised modules in verilog/system verilog. Classes can also be parameterised in the same way that modules are. This type of class definition provides a template of an actual class, definition of actual class will be created at the time of class instantiation.
Placeholder/template for parameterized class

class  asic_with_ankit  # (parameter int A = 1);
     bit [A-1 : data];

Actual class will be created when you instantiate the class with parameter value

asic_with_ankit  #(8)    awa ;

Data type also possible to pass as an parameter.

Class asic_with_ankit  #(type A = bit);
     A   register_bit;
     task register_update  (A  reg_update);

Nested Class:
Definitions appear inside the definitions of another class as it were a member of other class. In system Verilog you are allowed to use class within another class. Class declarations nested inside a class scope are public and can be accessible outside of the class.
Nested class helps increasing encapsulations and lead to more readable and maintainable code.
class A; 
     class B; // Nested class for a node in a linked list. 
          bit [7:0] reg; 
Typedef Class
Sometimes a class variable needs to be declared before the class itself has been declared.

For example,
typedef class ASIC_With_Ankit;
     class  AWA;
          ASIC_With_Ankit   AWA1;

“typedef class ASIC_With_Ankit;”  : typedef of class ASIC_With_Ankit allows compiler to process the class before it uses inside the class  AWA. This will avoid the compilation error otherwise  compiler will flag an error.

Hope this will be useful information on understanding of different classes in system verilog and their usage.

Happy reading ! 

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