Thursday, December 31, 2009

Industry's First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available

Dear Readers,

Industry's First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available

Low power design techniques have become increasingly complex and have led to an explosion in verification complexity, creating a need for a well-understood, robust, and reusable verification environment to achieve power goals and first-pass silicon success. The VMM-LP book documents the common causes of low power bugs, provides rules and guidelines for low power verification, specifies a SystemVerilog base class library facilitating the setup of a reusable verification environment, and recommends assertions and coverage techniques to accomplish comprehensive low power verification.

The methodology described in the VMM-LP book allows verification teams to attain coverage closure and pinpoint bugs using assertions. It can be implemented using voltage-aware static and dynamic verification tools, such as MVSIM with the VCS(R) simulator and MVRC, which are part of the Ecylpse(TM) low power solution from Synopsys. These tools are capable of checking low power designs for the rules documented in the VMM-LP book. The base classes will enable the infrastructure to create a structured and reusable verification environment based on the VMM-LP.

The VMM-LP book is available today for purchase through the VMM Central web site ( www.vmmcentral.org/vmmlp). Additionally, customers can download a PDF version of the book and register to receive notification about the availability of the source code for the VMM-LP SystemVerilog base classes from VMM Central.

Happy Reading,
ASIC With Ankit

Tuesday, October 13, 2009

Who should write Assertion, Designer or Verification Engineer?

Dear Readers,

Who should write Assertion, Designer or Verification Engineer?

The short answer is both. Generally, a designer will write assertions that go in the RTL, while the verification engineer will write assertions that are external to the RTL. For example, designers write assertions that are embedded in the RTL, while the verification engineer writes assertions on the interfaces of the design-under-test (DUT) and creates coverage points, checkers and monitors for the testbench. Verification engineers may also add assertions to fill any holes in the RTL checks left by the designer.

Controlling Assertions:

In any given DUT, there can be many assertions each consisting of one or more evaluation threads. Sometimes it is necessary to enable or disable certain sets of assertions. For example, during reset, all assertions not related to reset must be disabled, and during exception testing, the assertions related to the condition being violated must be disabled.

This means that a fine-grained mechanism must be defined for assertion control. One way to do this is to group assertions logically into categories. One or more categories can then be enabled or disabled at a time.

There are many different mechanisms available for assertion control. Each of the mechanisms has different trade-offs. $asserton/$assertoff system tasks are global mechanisms and can be used to control all assertions or specific named assertions. Compiler directives are compile time directives and allow assertions to be enabled or disabled at compile time. They do not allow assertions to be enabled or disabled dynamically during simulation.

SV has many strong construst and features through which engineer can confident and can say verification is nearly finished. But stil there are many questions comes to my mind are : 1. How do you ensure that there are enough assertions written? 2.How do you say that coverage what is written by you is 100% correct and covering correct behaviour or not?

I am eager to have some inputs on these questions, please share your views.

Happy Reading,
ASIC With Ankit

System Verilog Syntax highlighting for power point

Dear Readers,

Wouldn't it be great if we could colorize the code? would not it be a great if we could save .vim file in to .html with colors?

Many people migh know that we can store our current butter in .vim file with color and save it with the .html extension. If you still dont know how to do that, please do this: Run the following command in a syntax highlighted buffer:

:runtime! syntax/2html.vim

After typing this command, you’ll get a split window with your source in HTML. You can now save it to a file. This command saves the current buffer with a .html extension. Now you can open that extension in your favorite browser and you can copy the colorized text directly into PowerPoint!

Hope this is useful information.

Happy Learning,
ASIC With Ankit

Thursday, August 27, 2009

Assertions : What a powerfull feature of System Verilog..

Dear Readers,

SystemVerilog Assertions (SVA) are getting lots of attention in the verification community: Assertions are primarily used to validate the behaviour of a design. They may also be used to provide functional coverage information for a design..!

There are two types of Assertions in System Verilog :
1. Immediate Assertion
2. Concurrent Assertion

Both types have their own strong features, That all depens on our requirement which will decide which type of assertion we should use in our environment. But friendly speaking I would prefer Concurrent assertion most of the time as I found some of the advantages compare to Immediate assertion. And those advantage always encouraged me to use this type of assertions. Here I am listing down the advantages as per my experience:

1. Coverage statements (cover property) are concurrent and that's the reason we have used concurrent assertion as a part of our Test Bench. So it will be easy to dump a final coverage using this type of assertion with the strong System Verilog feature

2. The implication construct (|->) allows a user to monitor sequences based on satisfying some criteria, e.g. attach a precondition to a sequence and evaluate the sequence only if the condition is successful. There are two forms of implication: overlapped using operator |->, and non-overlapped using operator |=>.
3.User can use sequence to build complex properties.

These are the advantages which I came across so far in my experience on Assertions. I would be pleased if somebody can provide advantages of Immediate Assertion over Concurrent Assertions.

Assertions are providing strong verification features with which verification engineer can confident on his verificatoin environment and coverage using cover property with concurrent assertions.

Now you must be having a question that how assertions are effective with System Verilog?

In Verilog complex check requires complex verilog code, which will appear to be a part of RTL model to a Synthesis compiler, and one more disadvantage with Veriog is Assertion will active through out the simulation there is no simple way to disable all or some of the assertion during the simulation which is there in System Verilog, Now you should realize how effective it is Right ....? Means Asserstions can be controlled using system Verilog during the simulation.

One more strong feature which I have used is Assertion Binding, which is unique and powerful feature of System Verilog. Using this feature you can have your all assertion defined (coded) in separate TB file where you can have all required DUT as well as TB signals and registers with hierarchically from Top file. So that means without touching the RTL we can write assertion in separate file and that file will be included in our Test Environment.

As a Verification Engineer, I like Assertion, its strong and powerful in terms of Verification.

I would be pleased and thankful to you if you can share your experience on Assertions.

Happy Learning,
ASIC With Ankit

Monday, April 20, 2009

Interview Questions for ASIC

Dear Readers,

Here I would like to post some of the interview question which I have discussed with some senior engineers and industry experts. These are the questions most of the time interviewers asks. Here I will try to explain those all.

Que 1. What is setup and hold time? What will happen if there is setup and hold time violation?
[This question can also asked like "what is metastable state or what is metastability?"]

Ans 1.
Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.

Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

Que 2. What is the difference between latch and flipflop?
[This is the very basic question that most of the interviewer would like to ask to check basic fundamental of digital electronics]

Ans 2.
The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

Que 3. Build a 4:1 mux using 2:1 mux
[This is also a very basic question most interviewer would like to ask]

Ans 3. I would try to explain
Let say we have three 2:1 mux called A'B and C, So here we use two inputs of mux A and two input of mux B (total 4 input, which is the requirement to build 4:1 mux) and output of these two mux (A and B) will be 2 lines which will be input for third mux C. So we will be having 1 output from mux C. Now remaining thing is select line. We will hard wired selection line of A and B and called it as S0 and one select line will be used for mux C called S1. This way we can make a 4:1 mux using 2:1 multiplexer.

Que 4. Implement an AND gate using mux.

Ans 4. For AND gate give one input as select line. Incase if you are using B as a select line connect one input to logic 0 and one input to A.

Oue 5. In pure combinational Ckt, its necessary to mention all the inputs in sensitivity list? Is yes, Why?
Ans 5. Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

Hope this questions and answers are useful for the interested readers.

Happy Reading,
ASIC With Ankit

Thursday, April 16, 2009

JEDEC has announced eMMC4.4 standard

Dear Friends,

Here I would like to inform you regarding the Multimedia Card's new version specification as JDEC has now announced 4.4 on 14th April 2009. I am very excited to read the specification. I know now you might be surprised why I am so excited to read the same. The reason is I worked on verification of eMMC4.3 card IP.

JEDEC Announces Publication of new MMC v4.4 specification

* New Standard Features Performance and Security Features for Embedded Mass-Storage Flash Memory
* Widely Used in Mobile Phones, GPS, MP3 Players and Other Portable Electronic Devices

ARLINGTON, Va., USA – April 14, 2009 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD84-A44 MMC Version 4.4 standard. Continuing the evolution of e.MMC as an industry-leading memory technology, the new standard offers designers numerous enhancements including a doubling of the memory interface performance, flexible partition management and improved security options.

You can find this article from below given link:
http://www.design-reuse.com/news/20484/mmc-v4-4-specification.html

From this link you can also download the standard specification provided by JDEC.

Hope this is useful information for interested readers.

Enjoy,
ASIC With Ankit

Thursday, April 9, 2009

Seminar at NMG Polytechnic (ASIC with Ankit)

After a long time I got chance to represent myself as an presenter of technology in front of engineering students. As I have been in this field from more than 3 years I was exited to share my experience and importance of technology to the engineering students.

As I have finished my Diploma Engineering from N.M.G.P Institute (An ISO 9001:2000 certified), Kanara, Ranpur, http://www.nmgp.co.in/. I was planing to share my experience on technology in front of NMGP students and that's what I did in last week. It was thursday 2nd April when I suppose to go to NMGP for seminar on 'VLSI' and 'Importance of individual EC subjects in field or industries'.

I went there (NMGP) thursday morning with my power point presentation on my Lappy. As seminar timing was around 11:00 am, I had a time to visit NMGP building and recalled my old memories. I spent some time with old staff members and respected lectures who are still working with NMGP. At 11:00 am Seminar hall was ready with projector and my laptop setup. Students were also ready, taken their place and waiting for my presence on the stage with excitement !! I was too excited since it was my first presentation in front of 100s of engineering student !

I have started my presentation in front of EC engineering students and Sr/Jr Staff members (Lectures) of EC department. Agenda of that seminar was to give overview of VLSI technology and Importance of Digital Electronics in Industries. The goal was to create some interest for students on Digital fundamentals keeping in mind the industries requirement and technology growth !

Dear Readers,

Here I would like to share my some experience on my first seminar given to the polytechnic collage where I did my Diploma studies.

I was a student of the this polytechnic and I know most of the student's goal is to get good marks in the examination. But what I realized at this point is apart from mark there are something which each students should understand which is more important when you go for Job.

I explained the importance of Digital electronics in Chip Design and Verification. I have also explained latest VLSI Chip Technology with Transistor fundamentals by some examples and snap shots of some Chips. With this presentation I was trying to create self inspiration and motivation for engineering students. What I believe is "If you do things with your interest, things will be very easy and you can do it with smooth way".

Most interesting stuff of the seminar was two technology on which I worked in my past 1. USB OTG (USB On The Go) and 2. eMMC (Embedded Multimedia Card) Card IP (Intellectual Property) Verification. I have explained the application of those two technology and it was really interesting for students because they didn't know about these. I was glad after sharing this technology to students. Thanks to all those students who attended my session. It was full of excitement with lots of basic question answers session with students !

I hope with my efforts of presentation, some students might have started improving interest on engineering subjects, skills etc.... I have been receiving a many questions from students and answering their questions which could help them move ahead with their career. I would eagerly waiting to see somebody as an ASIC Engineer after some year down the road.

Thanks to NMGP Management, Sr/Jr Staff Members, Lecturers and students for their support and co-ordinations.

Visit their website (http://www.nmgp.co.in/) for Institute details.

Enjoy,
ASIC with Ankit

Monday, March 16, 2009

Basic Interview Questions for ASIC

Dear Readers,

In ASIC field, these are the most common questions people use to ask in interviews. So here I would like to share these type of questions with answers that can be useful to brush up fundamentals for ASIC engineer as well as any person who are using languages like Verilog, SystemVerilog, Vera etc...

Que : What is difference between Task and Function in Verilog?

Ans : The following rules distinguish tasks from functions:

  • A function shall execute in one simulation time unit;
  • A task can contain time-controlling statements.
  • A function cannot enable a task;
  • A task can enable other tasks or functions.
  • A function shall have at least one input type argument and shall not have an output or inout type argument;
  • A task can have zero or more arguments of any type.
  • A function shall return a single value; a task shall not return a value.


Que : How will you generate clock in Verilog?
Ans : There are many ways to generate clock in Verilog we could use one of the following:

Method1:
initial
   begin
     clk = 0;
   end
   always begin
     #5 clk =~clk ;
end

Method2:
initial
   begin
      clk = 0;
      forever begin
         #5 clk =~clk ;
      end
   end

Method3:
initial
   begin
      clk = 0;
   end
always begin
   #5 clk =0;
   #5 clk =1;
end

These are the ways which I know, there can be some other ways through which you can generate clock in Verilog. This peace of code can be useful for clock generation where you would like to generate clock.

I will keep updating some more question with answers. Please feel free to shoot me an email if you have any question and suggestions are always welcome. You can drop me an email with your feedback on asicwithankit@gmail.com

Happy Reading,
ASIC With Ankit