tag:blogger.com,1999:blog-29241554760045849732024-03-18T02:03:05.217-07:00ASIC With AnkitAnkit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.comBlogger76125tag:blogger.com,1999:blog-2924155476004584973.post-8552292351726224302023-06-28T01:08:00.004-07:002023-08-01T00:42:52.238-07:00Design Automation Conference 2023 (60DAC) at San Francisco - Lets meet, share, learn and network!<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9YzH_MlW4xFAjBzGQOVv_lznSkt81zUflJKAWiUgzVLosH0TOaR5IWVyUUPyb7PjAz4jOEwaimO_LkERjpNqbCxTjAXxpsbMR1jLf3EoKXvpuKjEa4nFpzAua8I_p80wyJFcq_D1MIo-evaSrvXmPVvEjHIWkJ_SvL0i4UpTtb5kHKBPl_TWyCQ7s9TI/s1355/230507CE_DAC120x60.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="559" data-original-width="1355" height="132" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9YzH_MlW4xFAjBzGQOVv_lznSkt81zUflJKAWiUgzVLosH0TOaR5IWVyUUPyb7PjAz4jOEwaimO_LkERjpNqbCxTjAXxpsbMR1jLf3EoKXvpuKjEa4nFpzAua8I_p80wyJFcq_D1MIo-evaSrvXmPVvEjHIWkJ_SvL0i4UpTtb5kHKBPl_TWyCQ7s9TI/w320-h132/230507CE_DAC120x60.jpg" width="320" /></a></div><br /><div class="separator" style="clear: both; text-align: center;"><br /></div><p></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;">Its an honor and privilege to share that I will be chairing <a href="https://60dac.conference-program.com/session/?sess=sess189" target="_blank">Front End Design session</a> at <a href="http://www.dac.com" target="_blank">60DAC</a><a href="https://www.dac.com/" style="color: #bb3300;" target="_blank"> </a>at San Francisco. Are you attending </span><a href="http://www.dac.com" style="font-size: 12.61px;" target="_blank">60DAC</a><span style="font-family: inherit; font-size: 12.61px;">? Let’s meet, share, learn and network.</span><span style="font-family: inherit; font-size: 12.61px;"> </span><a href="https://www.linkedin.com/posts/activity-7075362904518127617-JRAH?utm_source=share&utm_medium=member_desktop" style="color: #bb3300; font-family: inherit; font-size: 12.61px;" target="_blank">Details at LinkedIn post here</a><span style="font-family: inherit; font-size: 12.61px;"> </span></p><div class="separator" style="clear: both;"><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;"><br /></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;">Front Design Session for which I have given an opportunity to Chair <a href="https://www.dac.com/" style="color: #bb3300;" target="_blank">@DAC</a></p><p style="background-color: white; margin: 0in 0in 0in 27pt;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif" style="font-size: 12.61px;"><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif"><a href="https://60dac.conference-program.com/session/?sess=sess189">https://60dac.conference-program.com/session/?sess=sess189</a></span></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif"><br /></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJQ1McMO1mUjRncz7HHmgpUqa-v67xsUFmcaV1y0O3WgULFQjhfHEGEoo95XXk9mUJOrrAUNbYmoHFq-kFML5cqZ0Pkh6em-p-jNenFZ0-NY9Xt1iknQ47KkHs731S9eUBsqjlXSL9y36ZKR_XAuxvkFLDc7kGbXLL_AWE_ym-kBzWzUXCWM2r07FmiDY/s865/DAC_2023_SessionChair.pdf.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="865" data-original-width="847" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJQ1McMO1mUjRncz7HHmgpUqa-v67xsUFmcaV1y0O3WgULFQjhfHEGEoo95XXk9mUJOrrAUNbYmoHFq-kFML5cqZ0Pkh6em-p-jNenFZ0-NY9Xt1iknQ47KkHs731S9eUBsqjlXSL9y36ZKR_XAuxvkFLDc7kGbXLL_AWE_ym-kBzWzUXCWM2r07FmiDY/s320/DAC_2023_SessionChair.pdf.png" width="313" /></a></div><span style="font-size: 12.61px;"> </span><p></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif"><br /></span></p><div style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif">DAC Conference website for more details</span></div><div style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><a data-attribute-index="13" href="https://www.dac.com/" style="border: var(--artdeco-reset-link-border-zero); box-sizing: inherit; color: #bb3300; font-family: -apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif; font-weight: var(--font-weight-bold); line-height: inherit; margin: var(--artdeco-reset-base-margin-zero); padding: var(--artdeco-reset-base-padding-zero); position: relative; text-decoration: var(--artdeco-reset-link-text-decoration-none); touch-action: manipulation; vertical-align: var(--artdeco-reset-base-vertical-align-baseline);"><span style="color: black;">https://www.dac.com/</span></a></div><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;"><br /></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;">Check out my last years DAC visit details <a href="http://asicwithankit.blogspot.com/2022/07/my-visit-to-dac2022-with-summary.html" target="_blank">here</a></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><br /></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">The Design Automation Conference (</span><a href="https://www.dac.com/" style="color: #bb3300;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">DAC</span></a><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">) is recognized as the premier conference for design and automation of electronic systems. The conference is devoted to Electronic Design Automation (EDA), Intellectual Property (IP), Embedded Systems and Software (ESS), IoT, Automotive Systems, Artificial Intelligence and Machine Learning (AI/ML), Security and Design on Cloud. </span></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;"> </span><o:p></o:p></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="font-family: inherit;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">The 2023 Design Automation Conference (DAC 2023) will be held July 9–13 in San Francisco, CA, at the </span><a href="https://www.xplorit.com/san-francisco" style="color: #bb3300;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">Moscone Center West</span></a><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">.</span><span style="font-size: 12pt;"><o:p></o:p></span></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial; font-size: 10.5pt;"> </span><span face="Helvetica, sans-serif" style="font-size: 10.5pt;"><o:p></o:p></span></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;">If you are visiting DAC this year, lets stay in touch, I will be happy to meet, share and learn. Stay tuned for more details! </p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><br /></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><br /></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><br /></p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;">Thanks,</p><p style="background-color: white; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 12.61px; margin: 0in 0in 0in 27pt;"><a href="http://www.asicwithankit.com/" style="color: #bb3300;" target="_blank">ASIC With Ankit</a></p></div>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-1827753876049929232023-06-03T11:39:00.004-07:002023-06-05T19:19:17.602-07:00I am on Expert Circle by Criya! Lets meet, network, share and learn !<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRWd50dVSGwVeZjmvd1GZZg6Dp25KDcfLp5dEpBPb4pqOMoKXJcuDVuSm42MBMUFdv6OVRvG3enJF5-ahMGuSoqv5weH8IcjMu2LDUxBg1QtuRelzx7X5J3SOjU6EdKE8Qf3u-5ErfFBzgJQn_I0X14_-AdRxiTjVpSekUrCjigiH-WmanBJ48lKK5/s940/criya.jpeg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="788" data-original-width="940" height="335" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRWd50dVSGwVeZjmvd1GZZg6Dp25KDcfLp5dEpBPb4pqOMoKXJcuDVuSm42MBMUFdv6OVRvG3enJF5-ahMGuSoqv5weH8IcjMu2LDUxBg1QtuRelzx7X5J3SOjU6EdKE8Qf3u-5ErfFBzgJQn_I0X14_-AdRxiTjVpSekUrCjigiH-WmanBJ48lKK5/w400-h335/criya.jpeg" width="400" /></a></div><br /><div class="separator" style="clear: both; text-align: center;">ASIC With Ankit @<a href="https://www.criya.site/ankit" target="_blank"> Criya, Lets meet</a>!</div><p>Dear All,</p><p>I am excited to announce that I am on The Expert Circle by <a href="https://criya.site/ankit" target="_blank">Criya </a>(YC W22) - an invite only platform for industry leaders to share professional expertise and offer coaching, network, share and learn. After years of mentoring, coaching, interviewing, delivering webinars, seminars and presentations and helping professionals build successful tech careers, I am here to help more professionals reach their maximum potential.</p><p><a href="https://criya.site/ankit" target="_blank">Criya </a>founded by highly vetted network of top industry experts with powerful platform to share expert's expertise with industry. Feel free to book a call with me <a href="https://www.criya.site/ankit/appointments" target="_blank">(click here to book a call)</a>, get access to my resources or ask me for advice, guidance on various topics related to technology, tech career, through my <a href="https://criya.site/ankit" target="_blank">Criya </a>website. </p><p>Thank you all for being such a wonderful readers and providing your comments, messages and encouraging for writing interesting blog posts. I have been receiving many emails about discussing topics of mutual interest, mentorship, couching, guiding and just networking and helping each other by sharing knowledge from our expertise. </p><p>Please feel free to schedule <a href="https://www.criya.site/ankit/appointments" target="_blank">1:1 with me</a> and get access to my resources and ask advice, guidance on various topics related tech, career, mentorship, leadership, growth etc... Look forward to meet, share, learn and network! </p><p>Stay tuned for more updates and interesting blog posts!</p><p><a href="http://asicwithankit.blogspot.com/" target="_blank">ASIC With Ankit</a></p><p><br /></p><p><br /></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-81740017494768641892023-05-27T20:18:00.014-07:002023-05-27T23:54:19.717-07:00Semiconductor Ecosystem at a glance!<p>We all know semiconductor is the next growth story. we also seeing digital transformation of everything and in all industries, whether it is IOT (Internet of Things), AI (Artificial Intelligent), ML (Machine Learning), Automotive, Medical, Defense, 5G/6G, Networking, Cloud Computation or any retail business, Digital transformation is everywhere! </p><p>Here, I have tried putting things together to understand the Semiconductor Eco System in simple pictorial view below. </p><p></p><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEibkPB3R2oFN5ibr4hsybmD70rZa3bOMZ7jxS3KgGFOVuXcwVC86PPrv7oWTRUAN3hzisZTM1-Q39vG0YTMmt0sRKqhKt5XKWi7SIx4B5QFzskoBmE-zW5QIis_rQ1Dw6dqLqVqe2XGNfHT8NDnrAte--0l3WV5QTT-NB9ukAwVoC6PyKhDl8KTrnda" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="644" data-original-width="1102" height="234" src="https://blogger.googleusercontent.com/img/a/AVvXsEibkPB3R2oFN5ibr4hsybmD70rZa3bOMZ7jxS3KgGFOVuXcwVC86PPrv7oWTRUAN3hzisZTM1-Q39vG0YTMmt0sRKqhKt5XKWi7SIx4B5QFzskoBmE-zW5QIis_rQ1Dw6dqLqVqe2XGNfHT8NDnrAte--0l3WV5QTT-NB9ukAwVoC6PyKhDl8KTrnda=w400-h234" width="400" /></a></div><p class="MsoNormal"><span style="font-size: xx-small;"><b><span face=""Trebuchet MS", sans-serif" style="background: white; line-height: 107%;">Copyright ©
2023 </span></b><span style="line-height: 107%;">ASIC With Ankit @ www.asicwithankit.com</span><o:p></o:p></span></p><div style="text-align: left;">The semiconductor ecosystem refers to the interconnected network of companies, organizations, technologies, processes involved in the design, development, manufacturing and distribution, it also includes, universities which helps generated industry ready skill set for semiconductor industry. Now lets understand each component of this eco system.</div><div style="text-align: left;"><br /></div><div style="text-align: left;">Overall, This industry seems simple, Fabless Companies in semiconductor ecosystem design and develops chips. They give this design to foundries, Foundry then manufactures these chips and give them to OSAT and test packaging companies who then test, validate and puts them in to device to make it ready for end user.</div><div style="text-align: left;"><br /></div><div style="text-align: left;">Now, lets understand in detail how many types of companies are there in the whole eco system and what are different component makes the full ecosystem.</div><div style="text-align: left;"><br /></div><div style="text-align: left;"><b>1. IDM (Integrated Device Manufacturer):</b></div><div style="text-align: left;"><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEh8ifIW0eu3vqJOmZtVlW4yKDTfTMNp9jH4gZ0VsxkTXIZJWTIGQPJJTOnjslihM3_fK3MTp-CXbNbzqABzF7LeSJRxGk8lLaKtj007XUQxLG209ZgHISm5vmeWttZt3R7mfKn68fG0Z3GgCyw992vqev6_R6R8FxlwvL8RkgDAGagunxIgh3Hu1fkE" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="230" data-original-width="968" height="95" src="https://blogger.googleusercontent.com/img/a/AVvXsEh8ifIW0eu3vqJOmZtVlW4yKDTfTMNp9jH4gZ0VsxkTXIZJWTIGQPJJTOnjslihM3_fK3MTp-CXbNbzqABzF7LeSJRxGk8lLaKtj007XUQxLG209ZgHISm5vmeWttZt3R7mfKn68fG0Z3GgCyw992vqev6_R6R8FxlwvL8RkgDAGagunxIgh3Hu1fkE=w400-h95" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><span style="text-align: left;"><br /></span></div><div class="separator" style="clear: both; text-align: justify;"><span style="text-align: left;">A company that has all manufacturing processes and companies who design, develop and manufacture chips are called as IDM (Integrated Device Manufacturer). These type of companies has wafer producing facility, and also takes charge of in designing the semiconductors, wafer processing, packaging and testing. Basically from Semiconductor design to all the way manufacture! </span></div></div></div></div><div class="separator" style="clear: both; text-align: center;"><div style="text-align: justify;"><br /></div><div style="text-align: left;"><b>2. Fabless Companies:</b></div><div style="text-align: left;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEjLlCLxVwXkg6laY1rB50onUSE9DCS8fZuFlLhhjWPXru2kQafxVEvNKJKIKVeahbMXAssjwASp6K-KA5UrrmJk-zr1qmMjmc0F9O6QXB6v8uica9cVip4p4FXqMkR1U10RSihXRZQD2_p7mjJnTyFRPecQls874N-H_cKQqEc3ioyABRkBB87X9TGg" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="230" data-original-width="970" height="95" src="https://blogger.googleusercontent.com/img/a/AVvXsEjLlCLxVwXkg6laY1rB50onUSE9DCS8fZuFlLhhjWPXru2kQafxVEvNKJKIKVeahbMXAssjwASp6K-KA5UrrmJk-zr1qmMjmc0F9O6QXB6v8uica9cVip4p4FXqMkR1U10RSihXRZQD2_p7mjJnTyFRPecQls874N-H_cKQqEc3ioyABRkBB87X9TGg=w400-h95" width="400" /></a></div>A fabless companies are the one who focuses on designing semiconductor chips without factories that requires huge investment. Meaning companies which are producing wide range of products but in small or large amount and keep the technology diversity are called fabless companies. These companies requires TSMC, Intel and Samsung type companies who has their fabrication plants and can manufacture designed chips.</div><div style="text-align: left;"><br /></div><div style="text-align: left;"><b>3. Foundry:</b></div><div style="text-align: left;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEjhTnlG1TwEO2raem-g4LfPbsUYgPSHprsEFB3qKa1UfYYXJE7VdNDSgDTPfRLk852zdjQ2n-ack-zafqxdbqfNs1k9RUPeMh8wTeI-ObZR615oDRzmepTsheKb08KN6Rptdjs6oJwyyqog79_1cze7ljoMz9Edx610X_PpRyDRFrVV8kJSyPWq8rG1" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="229" data-original-width="969" height="95" src="https://blogger.googleusercontent.com/img/a/AVvXsEjhTnlG1TwEO2raem-g4LfPbsUYgPSHprsEFB3qKa1UfYYXJE7VdNDSgDTPfRLk852zdjQ2n-ack-zafqxdbqfNs1k9RUPeMh8wTeI-ObZR615oDRzmepTsheKb08KN6Rptdjs6oJwyyqog79_1cze7ljoMz9Edx610X_PpRyDRFrVV8kJSyPWq8rG1=w400-h95" width="400" /></a></div><br />A companies which only manufactures chips design received from fabless and IDM companies. So basically Foundry companies do not design and develop chips, they only manufactures chips. Instead of producing their own products they mostly take orders from fabless companies and manufactures chips for them. Producing semiconductor chips requires billions of dollar of investments and extremely complex production technologies, so its difficult for every semiconductor companies to do it on their own. So basically, foundries becomes the production facility for all these fabless companies.</div><div style="text-align: left;"><br /><b>4. OSAT (Outsourced Semiconductor Assembly and Testing):</b></div><div style="text-align: left;"><div class="separator" style="clear: both; font-weight: bold; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEjN5BdRMf7z2Ujkkb9OjXcyIP_zINDd_nwdrFzMwBZjKCg_7vjzZyy0SOzkIJv2zbTFgEHXH2992kXbpg1jZ46YFUm6NFju7odSlJGPjxOcq2DmNzpr0qNVw5ZJoR4w-I3PyfL_nZEamQIG4nQnOYiRVLJ7tJNGB_e8CvsvRfoMsE5eL4pWGjRW3hO_" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="227" data-original-width="967" height="94" src="https://blogger.googleusercontent.com/img/a/AVvXsEjN5BdRMf7z2Ujkkb9OjXcyIP_zINDd_nwdrFzMwBZjKCg_7vjzZyy0SOzkIJv2zbTFgEHXH2992kXbpg1jZ46YFUm6NFju7odSlJGPjxOcq2DmNzpr0qNVw5ZJoR4w-I3PyfL_nZEamQIG4nQnOYiRVLJ7tJNGB_e8CvsvRfoMsE5eL4pWGjRW3hO_=w400-h94" width="400" /></a></div><br />These companies are also called as Assembly or test packaging companies. Basically, it takes care of backend processes. In semiconductor industry backend processes are assembly and testing. Foundry manufactures the chips in to wafers but these chips can not exchange electric signals. Packaging are the process in which these chips are individually cut and packed to go in to devices. Now its time to check the quality of packed chips. So basically, OSAT companies are doing packaging and testing to make sure chips are working as expected and ready for end user.</div><div style="text-align: left;"><br /></div><div style="text-align: left;"><b>5. EDA (Electronic Design and Automation):</b></div><div style="text-align: left;"><b><br /></b></div><div style="text-align: left;">EDA company provides tools, technology and IPs for semiconductor designers to create, simulate and validate chip design. EDA companies plays important role in semiconductor ecosystem. EDA tools includes computer-aided design (CAD), simulation and verification software. Companies like Cadence, Synopsys, Mentor Graphics (Siemens Digital) and many other EDA companies, develops and provide these tools to help fabless and IDM companies to develop their chips fast and efficiently.</div><div style="text-align: left;"><br /></div><div style="text-align: left;"><b>6. Vendors, Suppliers and Distributors</b></div><div style="text-align: left;"><b><br /></b></div><div style="text-align: left;">There are vendors, supplier and distributors who help all of these companies to provide basic raw materials, tools, machines and also help sale chips and devices to end market.</div><div style="text-align: left;"><br /></div><div style="text-align: left;"><b>7. Universities and Training Institutes</b></div><div style="text-align: left;"><br /></div><div style="text-align: left;">Universities and training institutes also plays very important role in build strong semiconductor ecosystem. Universities develops and trained engineers and to make them industry ready so they can start contributing to semiconductor ecosystem. Without right skill development for engineers it becomes difficult for industry to get efficient output from engineers. So its very important for universities to collaborate and partner with industry to continuously learn about new technology, processes and require skills and adjust their curriculum.</div><div style="text-align: left;"><br /></div><div style="text-align: left;">The semiconductor ecosystem is highly complex and interconnected with each component relying on others to ensure the efficient and continues production and advancement of semiconductor technology. Collaboration with all partners, customers and all stack holder and robust supply chain is very important for the success of semiconductor industry.</div><div style="text-align: left;"><br /></div><div style="text-align: left;">You can watch my latest webinar to SVIT, university @Gujarat on Semiconductor overview and ecosystem. You can also subscribe to follow my <a href="https://www.youtube.com/@asicwithankit" target="_blank">YouTube Channel from here</a> </div><div style="text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: center;"><iframe allowfullscreen="" class="BLOG_video_class" height="266" src="https://www.youtube.com/embed/InGXrYSKAYI" width="320" youtube-src-id="InGXrYSKAYI"></iframe></div><div class="separator" style="clear: both; text-align: center;"><span style="text-align: left;"><br /></span></div><div class="separator" style="clear: both; text-align: center;"><span style="text-align: left;"><br /></span></div><div class="separator" style="clear: both; text-align: center;"><span style="text-align: left;">Hope this helps understanding Semiconductor ecosystem! Stay tunes for more interesting blogs!</span></div><div style="text-align: left;"><br /></div><div style="text-align: left;"><a href="http://www.asicwithankit.com" target="_blank">ASIC With Ankit</a></div><div style="text-align: left;"></div></div><p></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-9485356656122127592023-03-21T22:41:00.006-07:002023-03-21T22:43:12.473-07:00How to Randomize non-random variable in System Verilog<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhd35FST70DJV-LbK5p8k7sVFc7RJgPfo_HQQ9US7DA-fLF3mIjKgw5CutyFR3WMBnZ4cspbSsvEeRP97kVkdoq4yNmbAZ1AiXGMKTox1tiE4bEnD2io0s-h0cZhZ_bHDHbroOQwwSDgzOyHb9UvVt_HeK0SC4FRj-ReOtIydZn0E_pFd5JF8lbvUL-/s685/sv_randomization.jpeg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="608" data-original-width="685" height="284" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhd35FST70DJV-LbK5p8k7sVFc7RJgPfo_HQQ9US7DA-fLF3mIjKgw5CutyFR3WMBnZ4cspbSsvEeRP97kVkdoq4yNmbAZ1AiXGMKTox1tiE4bEnD2io0s-h0cZhZ_bHDHbroOQwwSDgzOyHb9UvVt_HeK0SC4FRj-ReOtIydZn0E_pFd5JF8lbvUL-/s320/sv_randomization.jpeg" width="320" /></a></div><br /><p>System Verilog is industry adopted very popular hardware descriptive language, most of the companies in industry have been using this language for complex SOC, ASIC design and verification.</p><p>System verilog has various ways you can randomize values and fields to generate random stimulus for complex system verification. Randomizing variables and fields which are declared as rand are easy to randomize with or without constraints. In system verilog you can just do <b><span style="color: #990000;">object.randomize()</span></b> and all variables and fields declared as rand will gets random values during the simulation. </p><p>There could be different situation where one require to know how to generate random values for variables which are not declared as rand? The answer is scope randomize function (<b><span style="color: #990000;">std::randomize()</span></b>)</p><p><b><span style="color: #990000;">std::randomize()</span></b> is a scope randomize function that enables users to randomize data in the current scope. This method is also very useful if some variables required to be randomized are not part of a class. </p><p>Lets understand this with simple example:</p><p><i><span style="color: #990000;">module my_module;</span></i></p><p><i><span style="color: #990000;"> bit [15:0] address;</span></i></p><p><i><span style="color: #990000;"> bit [31:0] data;</span></i></p><p><i><span style="color: #990000;"> function bit my_test ();</span></i></p><p><i><span style="color: #990000;"> bit pass;</span></i></p><p><i><span style="color: #990000;"> bit read_write;</span></i></p><p><i><span style="color: #990000;"> pass = std::randomize(address, data, read_write);</span></i></p><p><i><span style="color: #990000;"> return read_write;</span></i></p><p><i><span style="color: #990000;"> endfunction</span></i></p><p><i><span style="color: #990000;">endmodule</span></i></p><p>In this example, if you notice, we are using all these variables for scope randomize function. When you run this type of code usage, it <b><span style="color: #990000;">std::randomize</span></b> function will randomize all variables in its scope to generate random values without needing to use <b><span style="color: #990000;">.randomize()</span></b> method.</p><p>Now that we learn to randomize variable which are not rand in nature, you might have question what about constraints? How should we write constraints in this method. Good news is, you can. You can provide your constrains using "with" something like below:</p><p><i><span style="color: #990000;">pass = std::randomize(address, data, read_write) with {read_write -> address > 'h000F ;};</span></i></p><p>Hope you find this information useful. Stay tuned for more interesting stuffs about verification!</p><p><span style="color: #990000;"><a href="http://www.asicwithankit.blogspot.com" target="_blank">-ASIC With Ankit</a></span></p><p><br /></p><p><br /></p><p><br /></p><p><br /></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-9209005812942527172022-07-21T00:30:00.023-07:002022-07-23T11:13:19.120-07:00My visit to DAC2022 at San Francisco!<p><span style="font-family: inherit;"></span></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiC5b1Fjy0PJbTusYF9Fderu72PlxxDJR0KUhj_EPIfLaAd04Vfmn_DIlR_zicX4H0ckzGijvyLhYEOX8VBRyNWCs-caavz9Pgy25NguL748BqQLREe11qsEH2_PpEkjcLwKCmO6thM-U6z4ZEnm3YjiHOfapX5_blMmv2Au3NeirXX8cE0PaY6JSH_/s1920/WhatsApp%20Image%202022-07-23%20at%2012.09.24%20AM.jpeg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="1920" data-original-width="1920" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiC5b1Fjy0PJbTusYF9Fderu72PlxxDJR0KUhj_EPIfLaAd04Vfmn_DIlR_zicX4H0ckzGijvyLhYEOX8VBRyNWCs-caavz9Pgy25NguL748BqQLREe11qsEH2_PpEkjcLwKCmO6thM-U6z4ZEnm3YjiHOfapX5_blMmv2Au3NeirXX8cE0PaY6JSH_/s320/WhatsApp%20Image%202022-07-23%20at%2012.09.24%20AM.jpeg" width="320" /></a></div><div class="separator" style="clear: both; text-align: left;"><span style="background-color: white; font-family: inherit;">Design Automation Conference was held at Moscone Centre in San Francisco from 10 Jul 2022 to 14 Jul 2022. Abiding by COVID safety protocols, it was great to see in-person participation!</span></div><p><span style="font-family: inherit;"><span style="background: white;">The Design Automation Conference (</span><a href="https://www.dac.com/" style="background-color: white; color: #bb3300;"><span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;">DAC</span></a><span style="background: white;">) is recognized as the premier conference for design and automation of electronic systems. The conference is devoted to Electronic Design Automation (EDA), Intellectual Property (IP), Embedded Systems and Software (ESS), IoT, Automotive Systems, Artificial Intelligence and Machine Learning (AI/ML), Security and Design on Cloud. </span></span></p><p><span style="font-family: inherit;"><span style="background: white;"><span color="rgba(0, 0, 0, 0.9)">This year, DAC focused a lot on Machine/Deep learning & AI techniques, EDA on cloud and security verification. It was an </span></span><span style="background-color: white;">honor and privilege to share that I will be chairing Front End Design</span><span style="background-color: white;"> session at </span><a href="https://www.dac.com/" style="background-color: white; color: #bb3300;" target="_blank">59DAC</a><span style="background-color: white;"><a href="https://www.dac.com/" style="color: #bb3300;" target="_blank"> </a>at San Francisco. Are you attending </span><a href="https://www.dac.com/" style="background-color: white; color: #bb3300;" target="_blank">59DAC</a><span style="background-color: white;">?</span></span></p><p><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;">As demand for more application-specific chips increasing, the EDA community is relying on ML techniques. ML was discussed at the silicon level, where the industry is looking forward to developing more and more ML and neural networking processors and also discussed about using ML to optimize various aspects of the life cycle of semiconductor engineering.</span></span></p><p><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;">Many technical presentations and tech talks also covered the ML, There were panels to discuss how ML and AI could be used in design verification and implementation domains. </span></span></p><p><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;">Security verification was one of the key topic for which I was given opportunity to chair the session. Great presentation from different companies and university. Session topic was "New Developments in security verification and controlling unpredictable behavior" For details on this session <a href="https://59dac.conference-program.com/session/?sess=sess162" target="_blank">click here</a> & <a href="https://59dac.conference-program.com/presenter/?uid=947643" target="_blank">here</a></span></span></p><p></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIMXn3kTtBXQo5G-mOk_51o2XSK0KJ0AwjbKJdNVX-CwanrlYy6JGqT0Z0kZQkdmxTN5Ybot1hUIunNdTc1rG4QLo6e1MjJ8XdQW3Fv24oGEc-vTlRAH2K3huTCMojgHOnHHDyTImbUV-81sU9oYjaDfxtGQjg3lKKDwmi2NmUsFBDbuMCDHzJaYPL/s640/Session_chair.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="354" data-original-width="640" height="177" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIMXn3kTtBXQo5G-mOk_51o2XSK0KJ0AwjbKJdNVX-CwanrlYy6JGqT0Z0kZQkdmxTN5Ybot1hUIunNdTc1rG4QLo6e1MjJ8XdQW3Fv24oGEc-vTlRAH2K3huTCMojgHOnHHDyTImbUV-81sU9oYjaDfxtGQjg3lKKDwmi2NmUsFBDbuMCDHzJaYPL/s320/Session_chair.JPG" width="320" /></a></div><div class="separator" style="clear: both; text-align: center;"><br /></div><span style="font-family: inherit;"><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">Intel had <a href="https://www.intel.com/content/www/us/en/foundry/intel-foundry-services-at-dac-2022.html" target="_blank">Intel Foundry service booth at DAC</a> too! </span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><a href="https://www.intel.com/content/www/us/en/foundry/intel-foundry-services.html?wapkw=intel%20foundry%20services" target="_blank">Intel Foundry Services (IFS)</a>, have been engaging deeply with automotive OEMs to understand their foundry needs and how they can help support increasing demand and the industry’s transition to more compute-intensive applications. </span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">Intel Foundry Services (IFS) has also launched the Cloud </span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">Alliance, the newest addition to IFS Accelerator ecosystem. Through this alliance with key cloud providers and experts in electronic design automation EDA</span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">, Intel will ensure that manufacturing</span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"> customers have a more secure and more efficient process to bring their products to life. Some pictures from IFS booth at Intel</span></span><p></p><p></p><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhdy29tpQ7lNhtfmSzemSDnVlivxy0XltqEAecOftinZzUpdz021vd8DUXpWfTrXfueo4_X6wulXDqcfkH0LKnbjX6KyQcXhcDpGbKszT7KRRAe7TbjBFI6Ihw0QGlsdyOVaDVdQezlacvFBjNfiJdDhlHpafXdV9qntGOo-fwKiAIfQ7XU43sawnZy/s3000/20220712_094522.jpg" style="margin-left: 1em; margin-right: 1em;"><span style="font-family: inherit;"><img border="0" data-original-height="1868" data-original-width="3000" height="124" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhdy29tpQ7lNhtfmSzemSDnVlivxy0XltqEAecOftinZzUpdz021vd8DUXpWfTrXfueo4_X6wulXDqcfkH0LKnbjX6KyQcXhcDpGbKszT7KRRAe7TbjBFI6Ihw0QGlsdyOVaDVdQezlacvFBjNfiJdDhlHpafXdV9qntGOo-fwKiAIfQ7XU43sawnZy/w200-h124/20220712_094522.jpg" width="200" /></span></a></div><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEisxNVUMRhnk4vvI0QwnuUswTSxoGY_2nDhSB8svz0VxpcY-hh5oB9msmcUHFVUU5uiiUMdU9rUo2RLDbwPWt-MmmZWWrs6Sis3Erv1bqkUCgpjKfuIOymyXYiVOa-j0qY1p8luuJY0KyxuAbKEe9uCSBeKlGil2dTWPtem_2m0fHHWT-eEtzuSMtZh/s1841/20220712_094501.jpg" style="margin-left: 1em; margin-right: 1em;"><span style="font-family: inherit;"><img border="0" data-original-height="1721" data-original-width="1841" height="187" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEisxNVUMRhnk4vvI0QwnuUswTSxoGY_2nDhSB8svz0VxpcY-hh5oB9msmcUHFVUU5uiiUMdU9rUo2RLDbwPWt-MmmZWWrs6Sis3Erv1bqkUCgpjKfuIOymyXYiVOa-j0qY1p8luuJY0KyxuAbKEe9uCSBeKlGil2dTWPtem_2m0fHHWT-eEtzuSMtZh/w200-h187/20220712_094501.jpg" width="200" /></span></a></div><span style="font-family: inherit;"><div><span style="font-family: inherit;">Hon'ble Minister of Industries, Tamil Nadu, India. <a href="https://en.wikipedia.org/wiki/Thangam_Thennarasu" target="_blank">Mr. Thiru Thangam Thennarasu</a> held a meeting with </span><a href="https://www.linkedin.com/in/dr-randhir-thakur-747378/" style="font-family: inherit;">Dr. Randhir Thakur</a><span style="font-family: inherit;">, President, Intel Foundry Services and discussed the opportunities in the emerging semiconductor segment.</span></div><div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIgCgUmq-URFK8tgW3od6lDS-SHrN-HATw8EPOR3L5UULnBJGgEtY1fT5PDARXVRPiJeH6JBzmrBtcIoYTDmHmnzhWTK_ZDNzJOP7woI2EDzRCRugqkM_zJXpNiGb1xBm-zubiwUW87PjtW-GzrrITEruX5oaG-_S7HOYSdZkVgvDoxUmg6k7Q4lFJ/s1712/Randhir_Thiru.jpeg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="1712" data-original-width="1335" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIgCgUmq-URFK8tgW3od6lDS-SHrN-HATw8EPOR3L5UULnBJGgEtY1fT5PDARXVRPiJeH6JBzmrBtcIoYTDmHmnzhWTK_ZDNzJOP7woI2EDzRCRugqkM_zJXpNiGb1xBm-zubiwUW87PjtW-GzrrITEruX5oaG-_S7HOYSdZkVgvDoxUmg6k7Q4lFJ/w156-h200/Randhir_Thiru.jpeg" width="156" /></a></div></div><div>Intel had great present at DAC, <a href="https://www.linkedin.com/in/bobbrennan40/" target="_blank">Bob Brennan</a>, VP, GM, Intel Foundry Services, Customer Solutions Engineering had great presentation at Tech Talk DAC pavilion on "Open Architectures to Accelerate Industry Growth" <a href="https://www.linkedin.com/in/rahul-goyal-866333b4/" target="_blank">Mr. Rahul Goyal</a>, VP, VP, GM Intel Foundry Services was invited and participated in two successful event, DAC panel to discuss on important topic "Create Robust EDA & IP Ecosystems to strengthen the global semiconductor supply chain" and second one was Ansys Gold couch event, 1:1 interview with <a href="https://www.linkedin.com/in/john-lee-919a702/" target="_blank">John Lee</a>, GM and VP Ansys! Overall Great DAC2022!</div><div><br /></div><div><span style="font-family: inherit;">I also got an opportunity to meet industry experts, share and learn lot of exciting stuffs from them. Best part of the DAC this year from networking was to got and opportunity to meet very well known experts in semiconductor industry, </span><a href="https://www.linkedin.com/in/shiv-tasker-44911b/" style="font-family: inherit;" target="_blank">Mr Shiv Tasker</a><span style="font-family: inherit;">, Global Vice President, Semiconductor at Capgemini, </span><a href="https://www.linkedin.com/in/nitindahad/" style="font-family: inherit;" target="_blank">Mr. Nitin Dahad</a><span style="font-family: inherit;">, Editor in Chief of <a href="http://www.embedded.com">www.embedded.com</a> and corespondent for EETimes </span><span style="font-family: inherit;">and my good friend </span><a href="https://www.linkedin.com/in/hemmady/" style="font-family: inherit;">Mr. Shankar Hemmady</a><span style="font-family: inherit;">, Director at Intel Foundry Services. We had great chat at 39th floor at Marriot San Francisco. What a great meeting and conversation. Photo from our meet at Marriot, San Francisco. I like Nitin's post on LinkedIn, Click on the link to see what Nitin has to say about our meeting :) "</span><a href="https://www.linkedin.com/posts/nitindahad_embeddedsystems-systemverilog-eda-activity-6952785152464842752-BHM8?utm_source=linkedin_share&utm_medium=member_desktop_web" style="font-family: inherit;" target="_blank"><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">Influencers at </span><span style="background-color: white; border: var(--artdeco-reset-link-border-zero); box-sizing: inherit; font-weight: var(--font-weight-bold); line-height: inherit; margin: var(--artdeco-reset-base-margin-zero); padding: var(--artdeco-reset-base-padding-zero); position: relative; touch-action: manipulation; vertical-align: var(--artdeco-reset-base-vertical-align-baseline);">Design Automation Conference</span><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"> at the top of their game and on top of the world</span></a><span style="font-family: inherit;">"</span></div></span><p></p><p></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXP4OBPcBqNEt03ASE25wS9zqEoLTwt7H9Kjxb3K9zWN8SAoElfZQI4ll3H41NaeRmNIUvqCarXhn5yugpWr9m3GabVFEt7e_WJsE4X5afvLfwGw03jaK0v3LFq1sRSz2OPb5aBNiX9Jwlw_xNWp7JiW88n5iskTrpDLqYO2HUI6Ma9wmmwf-FQRBl/s1600/WhatsApp%20Image%202022-07-14%20at%202.01.46%20PM.jpeg" style="margin-left: 1em; margin-right: 1em;"><span style="font-family: inherit;"><img border="0" data-original-height="1200" data-original-width="1600" height="240" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXP4OBPcBqNEt03ASE25wS9zqEoLTwt7H9Kjxb3K9zWN8SAoElfZQI4ll3H41NaeRmNIUvqCarXhn5yugpWr9m3GabVFEt7e_WJsE4X5afvLfwGw03jaK0v3LFq1sRSz2OPb5aBNiX9Jwlw_xNWp7JiW88n5iskTrpDLqYO2HUI6Ma9wmmwf-FQRBl/s320/WhatsApp%20Image%202022-07-14%20at%202.01.46%20PM.jpeg" width="320" /></span></a></div><span style="font-family: inherit;"><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;">DAC is a place to meet your former colleagues. I had a great time catching up with them. It was also great to meet many engineers, customers, partners and industry experts. DAC also had interesting posters from young engineers from academic which was assuring that industry continue to evolve in safe hands. At DAC, I also met vendors! The vendors at their respective booths showed their new tools flows and methodologies (TFM), attracting audiences with their presentations, supporting talks, quizzes with some fun time and goodies :)</span></span><div><span color="rgba(0, 0, 0, 0.901960784313726)" style="font-family: inherit;"><br /></span></div><div><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;">Thank you, <a href="http://www.dac.com" target="_blank">DAC</a>! Thanks to all <a href="https://www.dac.com/About/2022-Committees/Designer-Tracks-Committee">DAC committee members</a>, organizer, sponsorers, contributors, partners and audience who participated to make this DAC a success ! Already waiting for DAC2023! </span></span></div><div><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;"><br /></span></span></div><div><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><span style="font-family: inherit;">Thanks,</span></span></div><div><span style="font-family: inherit;"><span color="rgba(0, 0, 0, 0.9)" style="background-color: white;"><a href="http://www.asicwithankit.com" target="_blank">ASIC With Ankit</a></span></span></div><br />Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-75102648185729095502022-06-24T16:17:00.003-07:002022-06-29T23:07:11.488-07:00Design Automation Conference 2022 (59DAC) at San Francisco - Lets meet, share, learn and network! <p> </p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjF4e3WiVFSulJuwtOTXXqM0G4sbWx77e77bT654PwFuqvsP-n_BSXEcAJf81L5VIlYGUO4oJYJP0HToWRN3kS3TLBrf4hSUyKwPsB0Ln_oCMXjcvRdyGy20e-gKUym7T7rWD0py8Dvx7C2YnT3oyuYpSXG0ga4H-BcdhgnG-K56JHaOfaWZhfW9Emy/s841/DAC_Session_Chair.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="841" data-original-width="768" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjF4e3WiVFSulJuwtOTXXqM0G4sbWx77e77bT654PwFuqvsP-n_BSXEcAJf81L5VIlYGUO4oJYJP0HToWRN3kS3TLBrf4hSUyKwPsB0Ln_oCMXjcvRdyGy20e-gKUym7T7rWD0py8Dvx7C2YnT3oyuYpSXG0ga4H-BcdhgnG-K56JHaOfaWZhfW9Emy/w365-h400/DAC_Session_Chair.JPG" width="365" /></a></div><div class="separator" style="clear: both; text-align: center;"><br /></div><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="font-family: inherit;"><span style="background-color: white;">Its an honor and privilege to share that I will be chairing Front End Design</span><span style="background-color: white;"> session at </span><a href="https://www.dac.com/" target="_blank">59DAC</a><span style="background-color: white;"><a href="https://www.dac.com/" target="_blank"> </a>at San Francisco. Are you attending </span><a href="https://www.dac.com/" target="_blank">59DAC</a><span style="background-color: white;">? Let’s meet, share, learn and network. <a href="https://www.linkedin.com/posts/activity-6943712043053043712-9Gud?utm_source=linkedin_share&utm_medium=member_desktop_web" target="_blank">Details at LinkedIn post here</a> </span></span></p><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="font-family: inherit;"><span style="background-color: white;"><br /></span></span></p><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="background-color: white;">Front Design Session for which I have given an opportunity to Chair <a href="https://www.dac.com/" target="_blank">@DAC</a></span></p><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="color: black;"><a data-attribute-index="11" href="https://lnkd.in/gZNgGtxi" style="background-color: white; border: var(--artdeco-reset-link-border-zero); box-sizing: inherit; font-family: -apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif; font-weight: var(--font-weight-bold); line-height: inherit; margin: var(--artdeco-reset-base-margin-zero); padding: var(--artdeco-reset-base-padding-zero); position: relative; text-decoration: var(--artdeco-reset-link-text-decoration-none); touch-action: manipulation; vertical-align: var(--artdeco-reset-base-vertical-align-baseline);">https://lnkd.in/gZNgGtxi</a><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif" style="background-color: white;"> </span></span></p><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif" style="background-color: white;"><br /></span></p><div style="margin: 0in 0in 0in 27pt; text-align: left;"><span face="-apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif" style="background-color: white;">DAC Conference website for more details</span></div><div style="margin: 0in 0in 0in 27pt; text-align: left;"><a data-attribute-index="13" href="https://www.dac.com/" style="background-color: white; border: var(--artdeco-reset-link-border-zero); box-sizing: inherit; font-family: -apple-system, system-ui, BlinkMacSystemFont, "Segoe UI", Roboto, "Helvetica Neue", "Fira Sans", Ubuntu, Oxygen, "Oxygen Sans", Cantarell, "Droid Sans", "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Lucida Grande", Helvetica, Arial, sans-serif; font-weight: var(--font-weight-bold); line-height: inherit; margin: var(--artdeco-reset-base-margin-zero); padding: var(--artdeco-reset-base-padding-zero); position: relative; text-decoration: var(--artdeco-reset-link-text-decoration-none); touch-action: manipulation; vertical-align: var(--artdeco-reset-base-vertical-align-baseline);"><span style="color: black;">https://www.dac.com/</span></a></div><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="background-color: white;"><span style="font-family: inherit;"><br /></span></span></p><p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="font-family: inherit;"><span style="background: white;">The Design Automation Conference (</span><a href="https://www.dac.com/"><span style="background: white;">DAC</span></a><span style="background: white;">) is recognized as the premier conference for
design and automation of electronic systems. The conference is devoted to
Electronic Design Automation (EDA), Intellectual Property (IP), Embedded
Systems and Software (ESS), IoT, Automotive Systems, Artificial Intelligence
and Machine Learning (AI/ML), Security and Design on Cloud. </span></span></p>
<p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="font-family: inherit;"><span style="background: white;"> </span><o:p></o:p></span></p>
<p style="margin: 0in 0in 0in 27pt; text-align: left;"><span style="font-family: inherit;"><span style="background: white;">The 2022 Design Automation Conference (DAC 2022) will be held
July 10–14 in San Francisco, CA, at the </span><a href="https://www.xplorit.com/san-francisco"><span style="background: white;">Moscone Center West</span></a><span style="background: white;">.</span><span style="font-size: 12pt;"><o:p></o:p></span></span></p>
<p style="margin-bottom: 0in; margin-left: 27.0pt; margin-right: 0in; margin-top: 0in; margin: 0in 0in 0in 27pt;"><span style="background: white; font-size: 10.5pt;"><span style="font-family: inherit;"> </span></span><span face="Helvetica, sans-serif" style="font-size: 10.5pt;"><o:p></o:p></span></p><p style="margin-bottom: 0in; margin-left: 27.0pt; margin-right: 0in; margin-top: 0in; margin: 0in 0in 0in 27pt;">If you are visiting DAC this year, please send me an email, I will be happy to meet, share and learn. Stay tuned for more details! </p><p style="margin-bottom: 0in; margin-left: 27.0pt; margin-right: 0in; margin-top: 0in; margin: 0in 0in 0in 27pt;"><br /></p><p style="margin-bottom: 0in; margin-left: 27.0pt; margin-right: 0in; margin-top: 0in; margin: 0in 0in 0in 27pt;">Thanks,</p><p style="margin-bottom: 0in; margin-left: 27.0pt; margin-right: 0in; margin-top: 0in; margin: 0in 0in 0in 27pt;"><a href="http://www.asicwithankit.com/" target="_blank">ASIC With Ankit</a></p><p></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-11285252005273880862021-12-27T16:07:00.003-08:002021-12-28T12:05:39.335-08:00System Verilog "ref" is a nice reference instead of "value"<p></p><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><img alt="" data-original-height="165" data-original-width="987" height="66" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiWj4wWdtlAki0r_ETwNsxheWKtARcbmu8YIk26klEUUEW0vTxJJX4QWXC6ZG2PASfnGn2Rkgx9Humh-2Wg4vTDfsp8Qp584Z7Y26IDf7hdoxFcGX-s4NMvD9LESTwuQqq92Hip_Gz5GbM/w400-h66/image.png" width="400" /></div><br /><br /></div>Pass by reference is an interesting and very useful feature in system verilog. Very useful and importatn topic to understand and you might hit this as interview question in your next verification interview. This one is one of the very commonly asked interview question. Lets understand...<p></p><p>To begin, lets understand basic concept for pass by value vs pass by reference. In verilog, method arguments takes as pass by value (this is default). The inputs are copied when the method is called and the outputs are assigned to relevant outputs when exiting the method. </p><p>In system verilog, methods can also have "pass by reference". In this case, arguments passed by reference are not copied into subroutine area instead, a reference to the original arguments are passed to subroutine. In this case subroutines can access the arguments data via reference. </p><p>This is very efficient way of passing arguments like class objects or arrays of objects. Scenario like these where you are dealing with class objects and arrays of objects, if you use pass by value it would create a consume lot of memory on the stack because it has to copy the values and then use it for subroutine. Another advantage of using pass by reference is, since the caller and the function/tasks shares the same reference, any change done inside function using reference would also be visible to the caller. </p><p>Example:</p><p><i>function automatic int my_crc (<b><span style="color: #cc0000;">ref </span></b>byte data [10:1]);</i></p><p><i> for (int j =1; j<=10; j++) begin</i></p><p><i> my_crc ^= data[j];</i></p><p><i> end</i></p><p><i>endfunction</i></p><p>In this example, you can see data is declared with "<b><span style="color: #cc0000;">ref</span></b>" meaning, each call to CRC in for loop, my_crc function does to need to create a copy of the data on stack memory. Memory would have been consumed more if you would not use "ref" and use it as pass by value (because in that case as mentioned, every time my_crc function calls, it would need to create a copy on stack memory)</p><p>Now, an obvious question!</p><p><b>What if user wants to make sure that the ref argument is not modified by the function?</b></p><p>Answer to this question is "<b><span style="color: #cc0000;">const ref</span></b>"!! We need to use <b><span style="color: #cc0000;">const </span></b>key word if you want to make sure that ref argument is not modified by the function. </p><p>For same example:</p><p>Same function "my_crc" the argument can be declared as "<b><span style="color: #cc0000;">const ref</span></b>" to make sure the original data contents are not modified accidently by my_crc function. Very very useful feature to understand in the case where you want to make sure engineers don't modified original content accidently. </p><p><i>function automatic int my_crc (<b><span style="color: #cc0000;">const ref </span></b>byte data [10:1]);</i></p><p><i> for (int j =1; j<=10; j++) begin</i></p><p><i> my_crc ^= data[j];</i></p><p><i> end</i></p><p><i>endfunction</i></p><p><br /></p><p>Now another obvious question!</p><p><b>Do we need to declare each arguments as "ref" if you have more than one argument in your task/function.</b></p><p>Answer is "NO". </p><p>For example:</p><p>task my_task (ref int data[10], bit a, b)</p><p>In declaration like this, one needs to clearly understand each arguments to function/task can have direction which can be input, output or inout or ref. If no direction specified the default value of inputs are selected. If one argument is specifies the direction then all following arguments hold on to the same direction unless explicitly changed.</p><p>In above example, my_task, first argument is specifies "ref" direction and following variables does not explicitly specifies direction, a and b would be considered as pass by reference.</p><p>Hope this clears out some basic understanding of pass by value vs reference. </p><p>Thanks,</p><p><b><span style="color: #cc0000;"><a href="http://www.asicwithankit.com/" target="_blank">ASIC With Ankit</a></span></b></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-52720428179890888292021-01-14T23:04:00.004-08:002021-12-28T18:48:27.157-08:00ASIC With Ankit on AMIQ and testbench.in's recommended list of blogs<p>Thank you <a href="https://www.amiq.com/consulting/resources/" target="_blank">AMIQ </a> and <a href="http://testbench.in/links.html" target="_blank">Testbench.in</a> for having ASIC With Ankit on recommended list of blogs.</p><p></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg8MXR5H93OOFP33JS_DKr4RDauxZl1azoWZV9uKLLjZOFvY0FfIwUHyOnxzrIj1ympHby7yYDqsesX4oHwvBHSQqKa1SAoKcjOuerk2TN70U07ZaUsPwFmK9CuqV9iWakK_RFK51Onp7g/s1024/WhatsApp+Image+2021-01-14+at+10.53.02+PM.jpeg" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="1024" data-original-width="1024" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg8MXR5H93OOFP33JS_DKr4RDauxZl1azoWZV9uKLLjZOFvY0FfIwUHyOnxzrIj1ympHby7yYDqsesX4oHwvBHSQqKa1SAoKcjOuerk2TN70U07ZaUsPwFmK9CuqV9iWakK_RFK51Onp7g/w400-h400/WhatsApp+Image+2021-01-14+at+10.53.02+PM.jpeg" width="400" /></a></div><p><br /></p><div class="separator" style="clear: both; text-align: center;"><br /></div>Learning is Sharing and Sharing is Learning too! Lets all keep sharing and keep learning!<p></p><p><a href="http://www.asicwithankit.com" target="_blank">-ASICWithAnkit</a></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-64180975118002279892021-01-14T17:09:00.002-08:002021-01-15T22:34:15.260-08:00System Verilog Array Randomization<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhMmjzDdiH6EtHE3s77fSLq2lp7kq2POJvWsxRG1pb_sWW_UXAFQVQWRReiqDmjAuA2QBittWtI-dGLedtPHhcrPoOQr-wdW5MQ7tXEB05qZKAfOjXio5a9y7bpwgLK8nQR_R18FnYbgvE/s685/WhatsApp+Image+2021-01-15+at+10.33.05+PM.jpeg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="608" data-original-width="685" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhMmjzDdiH6EtHE3s77fSLq2lp7kq2POJvWsxRG1pb_sWW_UXAFQVQWRReiqDmjAuA2QBittWtI-dGLedtPHhcrPoOQr-wdW5MQ7tXEB05qZKAfOjXio5a9y7bpwgLK8nQR_R18FnYbgvE/s320/WhatsApp+Image+2021-01-15+at+10.33.05+PM.jpeg" width="320" /></a></div><p>System Verilog has different types of arrays that you can
randomize to generate interesting scenario for the test bench you are working
on. In SV we mainly have static array ,dynamic array and also queues that you
can randomize, Lets deep dive in to each one of them to understand how you can
use it with system Verilog:</p><p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal"><u><b>Static Arrays:<o:p></o:p></b></u></p>
<p class="MsoNormal"><i><span style="color: #990000;">class my_static_array;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> rand bit [3.0] my_array [8]; <o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endclass<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">module my_testbench;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_static_array my_static_array_obj;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> initial begin<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_static_array_obj = new ();<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_static_array_obj.randomize();<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> $display (“my randomize value =%p”,
my_static_array_obj.my_array);<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> end<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endmodule</span></i><o:p></o:p></p>
<p class="MsoNormal">In above example, we have my_array declared as static array
which is declared as rand so that you array will be randomize when you do class
object.randomize in your module to generate random value for our static array,
You can play around with this example by changing different seed to how it
changes the random value w.r.t to different seed.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><u><b>Dynamic Array:<o:p></o:p></b></u></p>
<p class="MsoNormal">As we know, Dynamic arrays are the array for which size will
not be pre-determined during the declaration. Dynamic array declaration will
have square bracket [ ]. Lest deep dive in to example to better understand its
declaration and how you can randomize it:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><i><span style="color: #990000;">class my_dynamic_array;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">rand bit [7:0] my_array [] //dynamic array<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">//Adding some constraint to this array so we can constraint
array during randomization<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">constraint c1 {my_array.size >2 ; my_array_size <=10;}<o:p></o:p></span></i></p>
<p class="MsoNormal"><o:p><i><span style="color: #990000;"> </span></i></o:p></p>
<p class="MsoNormal"><i><span style="color: #990000;">//Constraint each array index value to be equal to index+1<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">constraint c2 {foreach (my_array[i])<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">
my_array[i] = i+1;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">
}<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">function void print_value ();<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> foreach (my_array[i])<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> $display(“my array value
my_array[%0d] = 0x%0h”, i, my_array[i] );<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endfunction <o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endclass<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">module my_testbench;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">my_dynamic_array my_dynamic_array_obj;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">initial begin<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_dynamic_array_obj = new(); //create a
memory for the class object<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_dynamic_array_obj.randomize();
//randomize class with constraint provided<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_dynamic_array_obj.print_value (); //calling
function from class to print array value<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">end<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endmodule</span></i><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Try this example and play around by changing constraint for
index value, array size and seed to see how it changes the value to create
corner scenario.<o:p></o:p></p>
<p class="MsoNormal"><br /></p>
<p class="MsoNormal"><u><b>Queue randomization<o:p></o:p></b></u></p>
<p class="MsoNormal">We can have a queue declared as rand and then later in test
bench you can randomize the queue to create a random value generate from the
queue elements, We can constraint and limit the queue size in the constraints.
Lets deep dive in to the example to better understand declaration of the queue,
how you can limit and constraint the size of the queue and how you can randomize
the queue to generate random behavior for your test bench:<o:p></o:p></p>
<p class="MsoNormal"><i><span style="color: #990000;">class my_queue_c;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">rand bit [3:0] my_queue [$] // Queue declaration with rand
to randomize it later<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">//constraint to limit the size of the queue<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">constraint c1 {my_queue.size() == 5;}<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endclass<o:p></o:p></span></i></p>
<p class="MsoNormal"><o:p><i><span style="color: #990000;"> </span></i></o:p></p>
<p class="MsoNormal"><i><span style="color: #990000;">module my_testbench;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">my_queue_c my_queue_c_obj;<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">initial begin<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_queue_c_obj = new ();<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> my_queue_c_obj.randomize ();<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> //Print values<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;"> $display(“my queue value =%p”,
my_queue_c_obj.my_queue);<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">end<o:p></o:p></span></i></p>
<p class="MsoNormal"><i><span style="color: #990000;">endmodule</span></i><o:p></o:p></p>
<p class="MsoNormal">Try this example and play around by changing constraint to
change size of the queue and seed to see how it changes the value to create
corner scenario.<o:p></o:p></p>
<p class="MsoNormal">Hope, this is useful simple example to understand
randomization of arrays. Stay tuned for more simple but exciting post to learn
System Verilog.<o:p></o:p></p><p class="MsoNormal">Keep reading and keep learning, stay tuned for more simple but exciting learning posts</p><p class="MsoNormal"><b><span style="color: #990000;"><a href="http://www.asicwithankit.com" target="_blank">-ASICWithAnkit</a></span></b></p>
<p class="MsoNormal"><o:p> </o:p></p>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-84653860261820168492020-06-07T23:54:00.005-07:002020-06-08T00:06:11.985-07:00Future of 5G looks bright!<div class="separator" style="clear: both; text-align: center;">
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<br />Dear Readers,<br /> <br /> Hope everyone are doing great, staying safe and healthy in this challenging time! The whole world these days are covered with unexpected challenge, we are all in this together and will come out from this together. We are strong together. First of all I would like to express Thanks from bottom of my heart to all the Doctors, Nurses and medical staffs, Paramedics, Police officers, Home care workers, grocery store personnel, Delivery people, transit workers, Airline worker and anyone who works with the public and making everyone's life moving.<br /> <br /> We all understand the typical and challenging situation around and we are together fighting strongly against and will come out from this too! We are together moving ahead with the new technologies like, IoT, Automotive, Artificial Intelligence, 5G networking, WiFi-6, Robotics, Health Care, Smart Cities, Connected Cars and many more technologies and applications. These days pretty much everything is very well accessed and in our palm through smart phones, internet and with 4G, LTE and 5G technology.<br /> <br /> As 5G technologies have been continuously evolving, it will certainly change the way we spend our lives, our communications will be faster than you can imagine, When you imagine a future powered by 5G, connected factory devices that “talk” to each other, mobile internet-connected to multiple devices at the same time, different vehicles communicating with the roads they travel on, and accessibility of information at unprecedented speeds will come to mind. <br /> <br /> Lot of companies are actively and aggressively working towards making 5G technology available for the world to connect quicker and faster. Once 5G is fully operational, there will no need for any kind of cable or wire to deliver entertainment or communications service to your mobile device, some companies have successfully introduced 5G-capable handsets, it might require more time for the proper availability of 5G. But it is expected that the maximum number of 5G connections would exist in the years to come. 5G is the future!! <br /> <br /> Thanks,<br /> <a href="https://www.blogger.com/#">ASIC With Ankit</a>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-77372353662616805852019-05-22T12:52:00.000-07:002019-05-22T12:52:09.065-07:00System Verilog Assertions (SVA) – Types, Usage, Advantages and Important Guidelines! <span style="font-family: inherit;">Dear Readers,</span><br />
<span style="font-family: inherit;"><br /></span>
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There was an article published by SmartPlay Technologies back in 2015 when I was working with them. It has very useful information to understand the usage, advantages, and guidelines about System Verilog Assertions (SVA).<br />
<br />
<span style="font-family: inherit;"><span style="background-color: white;">ASICs continue to grow in size and complexities and in this case, traditional verification techniques are not sufficient to achieve verification confidence. In complex designs, debugging simulations is an ever-increasing challenge. To address these challenges assertion-based verification is found. Design and Verification engineers can place assertions in design or bind to design which will be useful to monitor, report and take action when incorrect behavior is detected. Assertions are playing a major role in test bench development which helps to achieve maximum confidence on bug-free design. Moreover, it can be used in simulations as well as in formal verification. It enables engineers to leverage the strength for block level, subsystem level and for chip level verification in order to reduce the overall effort and efficient verification closure. System Verilog Assertions are setting up a viable and effective standard in design and verification. An assertion adds an advantage in the debugging process and makes complex simulation debug easy.</span></span><br />
<span style="font-family: inherit;"><br style="background-color: white;" /></span><span style="font-family: inherit;"><span style="background-color: white;">The introduction of SVA added the ability to perform immediate and concurrent assertions for Design as well as for Verification. Assertions are used to validate design whether it is working correctly or not. Assertions can be useful to make sure ‘How good is the test case?’ Furthermore, it provides a means to measure the quality of the verification process through the creation of coverage using cover property feature of System Verilog assertion.</span></span><br /><span style="font-family: inherit;"><span style="background-color: white;">Questions are </span></span><br />
<br />
<span style="font-family: inherit;"><br style="background-color: white;" /></span>
<span style="background-color: white;"><span style="font-family: inherit;">1. What type of System Verilog Assertions we have?</span></span><br />
<span style="background-color: white;"><span style="font-family: inherit;">2. Where to put these assertions in our test bench development? </span></span><br />
<span style="font-family: inherit;"><span style="background-color: white;">3. How </span><span style="background-color: white;">to implement these assertions?</span></span><br />
<span style="background-color: white;"><span style="font-family: inherit;">4. Usage, Advantage</span></span><br />
<span style="background-color: white;"><span style="font-family: inherit;">5. What are the important Guidelines for SVA implementation?</span></span><br />
<span style="background-color: white;"><span style="font-family: inherit;"><br /></span></span>
<span style="background-color: white;"><span style="font-family: inherit;">To find more details please read this blog post <span style="color: #990000;"><b><a href="http://www.asicwithankit.com/2014/08/system-verilog-assertions-sva-types.html" target="_blank">"System Verilog Assertions (SVA) Types, Usage Advantages and Important Guidelines" </a></b></span></span></span><br />
<span style="font-family: inherit;"><br /></span>
<span style="font-family: inherit;">Thanks,</span><br />
<span style="font-family: inherit;">Ankit</span>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-5787639656199798482019-01-02T02:01:00.000-08:002019-01-02T02:01:01.266-08:00Happy 2019!!<div class="separator" style="clear: both; text-align: center;">
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">2019 has finally arrived like every new year. A new year always bring new challenges in many fields which will allow us to learn and grow even more!! Best wishes on this new year from us!</span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">This time of the year is filled with moments of celebration, reflections, and resolutions- all of which are great for inspiration and making the necessary changes one has been thinking about in the past year. </span><span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">It is also the time to assess the year that has passed. So what happened during 2018 and what to do for a new year?</span></div>
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Lets all step back and self evaluate our self and list down all positive things that we think we are stronger and also list down weak points where we think we are lagging behind. Let's all try to focus on our weak areas and improve those. On this new year, let's all take some action items to work on and focus on improvements. I wish you all a happy new year, may this new year brings lots of energy to do more and more good things. </div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">Everybody expects life to have smooth way, nobody expects their life to have painful bumps like a 'ROLLER COASTER'! Things may go wrong in life, everything is up and down in life. Every year has new challenges and opportunities with lots of fun, learning !! Like every year this year was also an awesome year together. Let’s all step back for a few moments and think, list down all major good/bad events occurred to individual’s life. I must say… every event would teach you something to learn and accept a few things.. whether it is good or bad. Good events teach you how to share, celebrate and enjoy quality time while bad events teach you even more… like how to react, fight bad time, learn, accept and how to move forward with positivity. I strongly believe It’s a matter of how you look at it together.</span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">Everyone has their own learning and experience from the past year and new thinking, the expectation from the new year! Like everyone we also learn many things nice way while some hard way…..<b> but you learn in any case!</b><o:p></o:p></span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">I wish new year would be 1000 time better than the past year for everyone! May this year brings lots of happiness and energy to do more and more good things for family, friends, and society.<o:p></o:p></span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">Wishing you all very happy and healthy new year!!<o:p></o:p></span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">With Love,</span></div>
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<span style="font-family: "Trebuchet MS", sans-serif; font-size: 11.5pt;">ASIC With Ankit</span></div>
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Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-25699875103443493882018-11-08T11:36:00.000-08:002018-11-08T11:36:21.312-08:00Happy Diwali & Prosperous New Year!<div class="separator" style="clear: both; text-align: center;">
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<span style="color: blue; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;">Diwali is the biggest and the brightest festivals celebrated by families around the world. Deepavali (actual name of Diwali) means "a row of lights." This auspicious day is also known as the "festival of lights. There is a saying “A Happiness can be found from darkest of dark if one knows how to switch on the light”! </span><br style="color: #191919; font-family: "Trebuchet MS", Verdana, Arial, sans-serif; font-size: 15.52px;" /><span style="color: blue; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;"><br /></span><span style="background-color: white; color: #191919; font-family: "Trebuchet MS", Verdana, Arial, sans-serif; font-size: 15.52px;"></span><span style="color: blue; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;">The evil need not necessarily come in the form of demons, it can come as depression, desperation, and frustration which can cause more damage. Diwali is a reminder to slay all that is negative to our life. </span><br />
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<span style="background-color: white; color: #990000; font-family: "trebuchet ms", sans-serif; font-size: 15.3333px;">There is so much happening during this whole week, people start preparing for Diwali, shops (e-shops J) are full of sales and there is light all over. People celebrate Diwali with many other things like firecrackers, visiting friends and family places and having lots of sweets! Well, I miss those days celebrating Diwali with lots of firecrackers and lights on streets with friends. A lot of regulation here, but still we manage to celebrate with some of the crackers in our patio J One of these years, I am going to take a vacation to celebrate Diwali back hometown to renew my Diwali spirit. On Diwali days, people use to do colorful rangoli at their house.</span><br />
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<span style="color: blue; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;">Diwali is one of the biggest and brightest </span><span style="color: blue; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;">festivals<span style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial;"> in India and we do celebrate it with full of enthusiasm and happiness. I would like to celebrate this Diwali by expressing thanks to all my friends, family members, near and dear ones! You all are awesome and I am lucky to have you all in my life. </span></span></div>
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<span style="font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;"></span><br /><span style="font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;"></span><span style="color: #990000; font-family: "trebuchet ms", sans-serif; font-size: 11.5pt;">Diwali is the last day of Gujarati Year, Today, Vikram Samvat 2075 begins. So wishing you all a Happy New Gujarati Year. May this new year come with lots of happiness in your life.</span></div>
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Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-90341034074173094632018-09-22T23:56:00.001-07:002018-09-22T23:56:27.287-07:00System Verilog UVM Callbacks: Development and Usage<div class="MsoNormal">
<span style="color: #002060; font-family: inherit; font-size: 12pt;">What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.</span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;"><span style="font-family: inherit;">Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.<o:p></o:p></span></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;"><span style="font-family: inherit;">The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.<o:p></o:p></span></span></div>
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<span style="font-size: 12pt;"><span style="color: #990000; font-family: inherit;"><u><b>How to Define Callbacks?<o:p></o:p></b></u></span></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;"><span style="font-family: inherit;">First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:</span><o:p></o:p></span></div>
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<span style="color: #002060; font-size: 12pt;">Second thing, we need to do is to register the callback type with the type that will use the callback. This registration enables UVM to do type checking when a user tries to add a callback to a specific object.</span></div>
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<span style="color: #002060; font-size: 12pt;">If you miss the registration, UVM issues a warning that the callback type was not registered with the object type.</span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;">Now, let’s understand how you insert the callback.<o:p></o:p></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;">We will now insert a call to the callback functions in the code, UVM provides a utility macro to make the process very easy.<o:p></o:p></span></div>
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<span style="font-size: 12pt;"><span style="color: #990000;"><b><u>How to use Callback?<o:p></o:p></u></b></span></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;">Now we have callback class defined and can be used as necessary in the testbench to modify the generated data before its driven on DUT. Now, let’s see how we use it in the test bench. <o:p></o:p></span></div>
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<span style="color: #002060; font-size: 12pt;">Once this is done, you need to attach the callback to a specific instance from your test case and then run a test. With this implementation when you run your simulation, this callbacks will update/modify randomized packets before driver drives it to the DUT signals.</span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;">This type of mechanism is useful in many places such as for error injection, data corruption, missed transaction etc… <o:p></o:p></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;">Happy Reading,<o:p></o:p></span></div>
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<span style="color: #002060; font-size: 12.0pt; mso-bidi-font-size: 11.0pt;"><a href="http://www.asicwithankit.com/" target="_blank">ASIC WIth Ankit</a><o:p></o:p></span></div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-39938666359646230472017-08-08T18:18:00.000-07:002017-08-08T18:19:29.424-07:00UVM Sequencer and Driver - Basic concept<div class="MsoNormal">
A sequencer is an advanced stimulus generator that controls the items provided to the driver and then driver executes those items during the simulation.</div>
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<span style="line-height: 107%;"><br /></span> <span style="line-height: 107%;">Generator randomizes arrays of transactions and sequencer controls the generation of random stimulus by executing sequences. The sequence has the meaningful stream of transactions which can contain random data items, parameters and user can also add constraints. A user can combine sequences to create complex traffic streams.<o:p></o:p></span></div>
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<span style="line-height: 107%;">Now, let’s understand UVM Sequencer with some more details from very simple picture given below:<span style="font-size: 10pt;"><o:p></o:p></span></span><br />
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<span style="line-height: 107%;">Typically sequencer waits for <span style="color: #cc0000;">get_next_item()</span> call from a driver, randomize the item data and then sends the data item to the driver for execution. <o:p></o:p></span></div>
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<span style="line-height: 107%;"><u><span style="color: #cc0000;">How to create a sequencer?</span></u></span></div>
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<li>Derive sequencer from the uvm_sequencer base class and specify request and response type prameters<span style="line-height: 107%; text-indent: -0.25in;">.</span></li>
<li><span style="line-height: 107%; text-indent: -0.25in;">U<span style="line-height: 17.12px; text-indent: -0.25in;">se <span style="color: #cc0000;">`uvm_component_utils</span> and constructor</span></span></li>
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<span style="line-height: 107%;">With these, you can define the baseline for sequencer, with built in sequencers behavior you can generate a constrained random data with synchronizing driver and sequencers.<o:p></o:p></span></div>
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<span style="line-height: 107%;">Driver and sequencer are connected by way of TLM with driver’s seq_item_port connected to the sequencer’s seq_item_export. Sequencer produces data and sends them through se_item_export and driver consumes data itesm through its seq_item_port as shown in the figure above. A response is optional. Connections are made by components that contain instances of the driver and sequencers.<o:p></o:p></span></div>
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<span style="line-height: 107%;"><u><span style="color: #cc0000;">Handshake between Driver and Sequencer:<o:p></o:p></span></u></span></div>
<span style="color: #cc0000; line-height: 107%;"><u> </u></span><br />
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<span style="line-height: 107%;">Basic handshake is done using the task <span style="color: #cc0000;">get_next_tem()</span> and <span style="color: #cc0000;">item_done()</span>. Driver requests a randomized item from sequencer and block waiting for the sequencer to have an item available. When sequencer has an item available, it will provide it and the get_next_item() task will return this item. Driver signals the sequencer that the item was processed using item_done() after sending it to DUT.<span style="font-size: 10pt;"><o:p></o:p></span></span></div>
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<span style="line-height: 107%;">Simple Example:</span></div>
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<span style="color: #cc0000; line-height: 107%;">class my_sequencer externs uvm_sequencer #(my_pkt_transfer);</span></div>
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<span style="color: #cc0000; line-height: 107%;"> `uvm_component_utils (my_sequencer)</span></div>
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<span style="color: #cc0000; line-height: 107%;"> </span></div>
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<span style="color: #cc0000; line-height: 107%;"> function new (string name, uvm_component parent);</span></div>
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<span style="color: #cc0000; line-height: 107%;"> super.new (name, parent);</span></div>
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<span style="color: #cc0000; line-height: 107%;"> endfunction : new</span></div>
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<span style="color: #cc0000; line-height: 107%;">end class : my_sequencer</span></div>
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Let's understand sequencer from example sudo code:</div>
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`uvm_component_utils macro is used to register sequencer with the common factory. In the class definition above, by default, the response type is the same as the request type. If you expect the different response, an optional second parameter must be specified for the uvm_sequencer.</div>
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something like...</div>
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<span style="color: #cc0000;">class my_sequencer externs uvm_sequencer #(my_pkt_transfer, my_pkg_response);</span></div>
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These are basic things to understand sequencer and definition of the sequencer to use it with the driver. We will continue on this for driver part and communication with Driver.</div>
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Hope, this is useful and clears some basic facts about sequencer and its usage. Feel free to shoot me an email asicwithankit@gmail.com for any question on this or would like to understand more on this.</div>
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Happy Reading,</div>
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<a href="http://www.asicwithankit.blogspot.com/" target="_blank"><span style="color: #cc0000;">ASIC With Ankit</span></a></div>
</div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com5tag:blogger.com,1999:blog-2924155476004584973.post-38249280337324981422015-11-22T14:46:00.002-08:002015-11-22T14:49:25.636-08:00System Verilog Assertion Binding - SVA Binding<div class="MsoNormal">
Dear Readers,<br />
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As we all know SV has become so popular in verification industry with its very good features and constructs which helps us verify today's complex designs. Today, I am going to discuss about SVA binding that we use in test bench for SVA properties.<br />
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There are VHDL and Verilog model we use to deal with these
days. Mostly verification engineers are not allowed to modified these modules.
But still SVA addition to these modules are required and easy to verify lot of
RTL functionality. How can you add SVA to these modules? </div>
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Here is where system verilog ‘<b><span style="color: #cc0000;">bind</span></b>’
comes in picture. Generally you create a SVA bind file and instantiate sva module
with RTL module.<o:p></o:p></div>
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SVA bind file requires assertions be wrapped in module that includes
port declaration, So now lets understand this with a small example to understand basic things on how to use SVA bind : </div>
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<span style="color: #cc0000;"><span style="font-size: x-small;">click on below image to enlarge.. </span><o:p></o:p></span></div>
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<span style="color: #cc0000; font-size: x-small;">DUT_Module - Dummy RTL module to understand this example</span></div>
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<span style="color: #cc0000; font-size: x-small;">SVA_Module - Dummy SVA module with implemented assertion property</span></div>
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<span style="color: #cc0000; font-size: x-small;">TB_Module - Dummy test bench code to see how bind works with module instantiation</span> </div>
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Here, you could see there is DUT instantiation created <span style="color: #cc0000;"><b>DUT_u1 </b></span>instance of <b><span style="color: #cc0000;">DUT_Module</span></b>. Now point of interest for us would be, how to bind DUT instance
to SVA module.</div>
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<o:p></o:p></div>
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To understand this take a look at line number <b><span style="color: #cc0000;">50 </span></b>in image from <b><span style="color: #cc0000;">TB_Module</span></b>, where you
could see 'bind' keyword used with <b><span style="color: #cc0000;">DUT_Module </span></b>module and <b><span style="color: #cc0000;">SVA_Module</span></b>. This is the place
where we are binding DUT module with SVA module. Thus passing DUT signal
information to SVA module. With this we could play around with DUT signal and can check assertion properties using DUT signals available through this
instantiation.</div>
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<o:p></o:p></div>
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If the assertion module uses the same signal names as the
target module, the bind file port declarations are still required but the bind-instantiation
can be done using the SystemVerilog <b><span style="color: #cc0000;">.* </span></b>implicit port connections. If signal names are not exactly matching between target and bind file module then we need to expand the instantiation with respected port names.<o:p></o:p></div>
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Hope, this information on SVA binding is useful, stay in touch with me and share your views !<br />
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Thanks,</div>
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<b><a href="http://www.asicwithankit.blogspot.com/" target="_blank"><span style="color: #cc0000;">Ankit Gopani</span></a></b></div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-50199376804713495432015-03-08T19:35:00.000-07:002015-03-08T23:22:52.045-07:00System Verilog : Functional Coverage Guidelines<div class="separator" style="clear: both; text-align: center;">
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<span style="text-align: start;">We have been implementing every possible checks to make sure design is verified but what have we done to check our test bench ? How do we make sure that our test bench has covered everything that needs to be covered w.r.t to specification and test plans ? Here is the place “Functional Coverage” and “SVA” comes in picture!</span></div>
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<span style="text-align: justify;">Before we start on few guidelines to follow while working with functional coverage, I would encourage you to refer various posts on functional coverage and assertions to get high level idea on architecture and usage. Click on </span><a href="http://asicwithankit.blogspot.in/2011/01/coverage-model-in-system-verilog-test.html" style="text-align: justify;" target="_blank">1,</a><span style="text-align: justify;"> </span><a href="http://www.asicwithankit.blogspot.com/2012/12/system-verilog-functional-coverage.html" style="text-align: justify;" target="_blank">2,</a><span style="text-align: justify;"> </span><a href="http://www.asicwithankit.blogspot.com/2013/01/the-two-door-keepers-assertion-to-make.html" style="text-align: justify;" target="_blank">3!</a><span style="text-align: start;"></span><br />
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Now, Basic questions can come to mind is, "what is the difference between code and functional coverage?". Let’s understand it at high level and then we will move forward to understand guidelines for functional coverage.</div>
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<span style="color: black; font-family: Calibri; font-size: small;">Sr No</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">Code Coverage</span></div>
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<span style="font-family: Calibri;"><span style="color: black; font-size: small;">Functional Coverage</span><span style="color: black; font-size: small;"> </span><span style="color: black; font-size: small;">and SVA</span></span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">1</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">Derived from design code with the help of simulation tools</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">It is user specified, controlled approach coverage by test bench</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">2</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">Evaluate design code to check whether structure is covered or not</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">Measures functionality part with the help of covergroup, cover point and bins (with the help of luxury feature of System Verilog </span><span style="font-family: Wingdings;"><span style="color: black; font-size: small;">J</span></span><span style="color: black; font-family: Calibri; font-size: small;">)</span></div>
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<span style="color: black; font-family: Calibri; font-size: small;">(With SVA you can capture functional coverage using cover property)</span></div>
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To conclude with few guidelines from various posts on functional coverage and assertions:<br />
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Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Verification engineers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closer. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test environment should be random and intelligent enough to make sure design is covered as a part of code coverage and designer should be in agreement while code coverage review. There should be valid comments with reason for all exclusions for code coverage w.r.t to design specification. Functional coverage should be written such a way that it should be able to capture all identified functionality while defining the test plan. Coverage and assertions are very important entity in the verification process and there are few guidelines that would help in verification process.<br />
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Few guidelines while working with functional coverage<br />
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<li>Your test plan should be based on the functionality you want to verify w.r.t to specification</li>
<li>You should have a coverage matrix with the list of cover point details w.r.t to your test plan scenario and there should be link of traceability between test scenario and cover point.</li>
<li>Environment should have control mechanism for enabling or disabling coverage and assertions for better control ability in your environment</li>
<li>Don’t enable functional coverage at the beginning of the verification to avoid simulation overhead in the starting phase of verification</li>
<li>During the initial time of the verification bug ration is typically high, as you move forward to the verification bug ration would start to drop. Here is the time when you should enable coverage and analyze it</li>
<li>Functional coverage plan needs to be updated as verification progresses</li>
<li>As your knowledge of the design and corner case understanding increases, you should keep updating your functional coverage plan</li>
<li>Make effective use of cover group “trigger” and sampling mechanism. (Stay tune for sampling mechanism on upcoming blog post !)</li>
<li>Follow meaningful names of cover group and cover points. This will help when you in debug process</li>
<li>Coverage should not be captured on failing simulations. Make sure to gathered coverage for only passing simulation. If few tests are not passing in regression first make sure to fix those issues before come to a conclusion on coverage achievement</li>
<li>If your tests are keep exercising the same logic in design, start developing the new tests for uncovered coverage part of coverage (coverage holes)</li>
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For guidelines on SVA, please refer to <a href="http://www.asicwithankit.blogspot.com/2014/08/system-verilog-assertions-sva-types.html" target="_blank">this article</a> !<br />
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Stay tuned to understand functional coverage sampling mechanism !<br />
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Thanks,<br />
<a href="http://asicwithankit.blogspot.com/" target="_blank"><span style="color: #990000;">ASIC With Ankit</span></a>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com1tag:blogger.com,1999:blog-2924155476004584973.post-24432990457296231272014-12-19T19:08:00.000-08:002014-12-19T20:18:34.300-08:00What a 'logic' you have System Verilog !!<div class="separator" style="clear: both; text-align: center;">
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Before we understand the “logic” data type for system Verilog, Lets understand verilog data types “reg” and “wire”. Wire is used to connect gates or modules and are physical wire in a circuit and it must be driven by a continues assignment statements. “Reg” in Verilog is a data object that holds its value from one procedural statement to next. When we say "reg (register datatype)" it does not mean the register in the hardware or a physical register in circuit. This is the common mistake or assumption mostly engineers thinks while learning Verilog.<br />
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In System Verilog, it improved the classic “reg” data type so that it can also be driven by continues assignments. The name they given for data type is “logic” in System Verilog. It is 4 state (1, 0, X, Z) System Verilog data type.<br />
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Let’s take an example to understand the usage of logic data type<br />
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Example :<br />
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<em><span style="color: #990000;"><strong>module</strong> Asic_With_Ankit (input logic xyz);<br /><br /> <strong>parameter</strong> DELAY;<br /> <strong>logic</strong> a, b, c;<br /><br /> <strong>initial</strong> <strong>begin</strong><br /> a = 0;<br /> <strong>forever</strong> #(DELAY/4) a = ~a<br /> <strong>end</strong></span></em><br />
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<em><span style="color: #990000;"> <strong>assign</strong> c = ~c;<br /><br /> <strong>endmodule</strong></span></em><br />
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In above example, you can see statement “a = 0” is procedural assignment while statement “assign c = ~c” is a continues assignment. So the important point to understand here is “SV allowed continuous assignments to logic variables, whereas in Verilog, you can’t use continuous assignments to “reg” variables”<br />
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“logic” signal can be used anywhere a “net” used but there is one exception to this, you can not drive logic variable from multiple driver. In these type of cases, variable needs to be a net type such as “wire” so that SV can resolve the multiple values.<br />
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Logic type can only have a single drive, it can’t allowed multiple driver. This means we can declare all signal as logic to find if is there any multiple driver issue. Because in this case you should be able to see compilation issue if there is any multiple driver by declaring all signal with type “logic”. Of course for the signal you would like to have multiple drivers shall be declared as net type such as “wire” or “tri”.<br />
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So, logic data type is identical to “reg” in every way except in SV it improved reg with logic so that it can also be driven by continues assignment and there would not be any confusion on “reg” data type w.r.t to physical register in hardware J<br />
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Enjoy,<br />
<a href="http://asicwithankit.blogspot.com/" target="_blank"><span style="color: #990000;">ASIC With Ankit</span></a>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com1tag:blogger.com,1999:blog-2924155476004584973.post-78897567671186064492014-11-10T22:10:00.001-08:002014-12-15T01:39:39.457-08:00System Verilog Class : No numbers for class name please !<div class="separator" style="clear: both; text-align: center;">
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Dear Readers,<br />
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Today I am going to share you one limitation with system Verilog class definition. We know Class is the basic feature to understand if we have to learn System Verilog. Class is the basic construct, data type in System Verilog. Some of the class feature I highlighted in my couple of previous blog posts can be found from <a href="http://asicwithankit.blogspot.in/2013/08/class-classical-feature.html"><span style="color: #990000;">here </span></a>and <a href="http://asicwithankit.blogspot.in/2014/04/class-classic-feature-part-ii.html"><span style="color: #990000;">here</span></a>.<br />
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Methodological approach to name system Verilog class and major advantages<br />
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As a verification engineer with a mindset of methodological test bench architecture we prefer to name all data types, variables, blocks with meaningful names and their objects so that anybody with little understanding of that environment will be easily able to understand why is that class defined or what is the significant of adding this parameter? Let me give you a small example:<br />
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For example, a team of 3-5 engineers have developed a complex SoC or Block level verification environment using system Verilog. Environment is such complex that it has many classes defined to perform certain functional verification. Now with methodological approach usually engineers defined their test environment by classifying various configurable parameters and feature control and transaction based features and they will develop environment to accommodate these features in respected class called configuration class and transaction class respectively. They have given a names for cfg and transaction class to “rx_dma_cntrl_cfg” and “rx_dma_cntrl_tr”. Here “_cfg” represents configuration class while “_tr” represents transaction class which is quite common approach in today’s test bench developments.<br />
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Why do we need to follow these type of small-small things?<br />
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Well, answer to this question is “there are many advantage of following these type of approach while developing your test environment at the same time it does not cost you much”<br />
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<span style="color: #990000;">Advantages:</span><br />
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<li>It helps in debugging the complex test environment as we all know “debugging is not free” and it always consumes amount of time and bandwidth in the verification cycles but we can always try to reduce the debugging efforts by following these small steps.</li>
<li>Helps engineer to understand environment structure. This will be more helpful when new person joins in the team to work on this type of developed environment. It will surely reduce the reamp-up time for engineer and can easily pick up the tasks to update/modify/enhance such type of test bench environments.</li>
<li>Helps in maintenance, enhancement and for re-usability</li>
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<span style="color: #990000;">Limitation (while naming meaningful name to class)</span><br />
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We cannot name class starting with numeric number like 0,1,2 etc.. ! Class name is not allowed to have numbers as first character. Meaning you can’t give a class name called “8_bit_dma_env” or “8bit_dma_env”. Simulation will throw an error if you use this approach, instead it can be defined like “eight_bit_dma_env” or “dma8_bit_env” this is allowed because you are not using numeric number as first character of class name.<br />
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Let’s take an example of small exercises to understand :<br />
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<span style="color: #990000;"><b>program </b>ASIC_With_Ankit;<br /><br /> <b>class </b>1_byte_display_test;<br /><br /> <b>int </b>a;<br /> <b>byte </b>awa = 8'hA5;<br /><br /> <b>task </b>display ();<br /><br /> <b>$display </b>("Byte value =%h", awa);<br /><br /> <b>endtask </b><br /><br /><b>endclass</b><br /><br /><b>initial begin</b><br /> 1_byte_display_test bdt;<br /><br /> bdt = <b>new </b>();<br /> bdt.display ();<br /><br /><b>end</b><br /><b>endprogram</b></span><br />
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<span style="color: #990000;">Solution :</span><br />
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In above example, you can see the class name uses first character as numberic number “1” which is not allowed in system Verilog and when you try compiling this code, you will see an error given below. But if you try the same example with changing a name to “one_byte_display_test” or “byte1_display_test”, you would be able to compile the same exercises without error<br />
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<span style="color: #990000;">#################### ERROR ######################<br />-- Compiling program ASIC_With_Ankit<br />** Error: <a href="http://class.sv/"><span style="color: #990000;">class.sv</span></a>(3): near "1": syntax error, unexpected "INTEGER NUMBER", expecting "IDENTIFIER" or "TYPE_IDENTIFIER"<br />################################################</span><br />
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Hope this is useful information, keep reading “ASIC With Ankit” !<br />
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<span style="color: #990000;">Enjoy !<br /><a href="http://www.asicwithankit.blogspot.com/" target="_blank"><span style="color: #990000;">ASIC With Ankit</span></a></span>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-38028926144998451732014-10-19T17:08:00.001-07:002015-05-28T11:26:36.136-07:00Semiconductor Acquisistion - Mergers - Takeover and Impacts<div class="MsoNormal" style="background: white; text-align: left;">
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Dear Readers,<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Mergers and acquisition are common in today’s global market. If
you take a history of any successful big companies in the market for more than
10-15 year, you would see the list of companies they acquired. So now two questions
comes in mind. </span><span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">"Companies does acquisitions and become successful in the market?
Or Successful companies does acquisition to be in market with profitable
approach YoY?"</span></span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">. There could be a different answers to these question depending
upon various factors. I would be pleased to hear answers/views on these questions. Lets share views and experience.<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Let’s assume that acquisition is part and process for successful
companies and try to understand what impact does it make on different segments.<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">These days you might be observing industries’ various deals in
terms of either merger, acquisition or takeover with all sets of new brand names.
It is a way for companies to acquire technology, products and man power to
improve profit and stock price while reducing overall expenses. In last few
months, I have heard about many small to big acquisition in 2014. Some of them
are given below in table and many more could be in the pipeline or in process.<o:p></o:p></span></div>
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<b><u><span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Some of the recent acquisitions-mergers
happened in 2014-15:</span><span style="color: #222222;"><o:p></o:p></span></span></u></b></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Avago<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">LSI - Broadcom</span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Inphi<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Cortina<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Infineon<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">International
Rectifier<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Seagate<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">LSI’s Flash business
unit<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">ON Semiconductor<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Aptina Imaging<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Qualcomm<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Wilocity, Black Sand
Tech, HP Patents and CSR plc<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Synopsys<o:p></o:p></span></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">Coverity<o:p></o:p></span></span></div>
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<u><span style="font-family: Arial, sans-serif; font-size: 10pt;"><b><span style="color: #990000;">Impacts:</span></b><span style="color: #222222;"><o:p></o:p></span></span></u></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Lets understand what are the segments where mergers/acquisition could
make an impact. There are two major segments where we could see the small to
major impact because of acquisition and mergers.<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">1.</span><span style="color: #222222; font-family: "Times New Roman","serif"; font-size: 7.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: "Times New Roman","serif"; font-size: 7.0pt; mso-bidi-font-size: 11.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Service/consulting/Contract/Freelance<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">2.</span><span style="color: #222222; font-family: "Times New Roman","serif"; font-size: 7.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: "Times New Roman","serif"; font-size: 7.0pt; mso-bidi-font-size: 11.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Employees<o:p></o:p></span></div>
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<u><span style="font-family: Arial, sans-serif; font-size: 10pt;"><b><span style="color: #990000;">Service/consulting/Contract/Freelance:</span></b></span></u><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";"><o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Service segments who mostly relies on the product based
companies for business revenue may face a challenge to gain business. During
the merger/acquisition time most of the companies holds/stops their decisions for
outsourcing their work to service companies. There are strong reason behind
holding these decisions as they expect man power, technology and product
acquisition as a part of merger/acquisition deal. So management has to think
and restructure all sets of resources to make sure effective and profitable
utilization model in place. Only after concluding this model they can either
release, postpone, cancel their decision on outsource/contract the work. This
could eventually effects service business revenue, consulting and contracting
opportunities for freelancers. Would be happy to hear from experts on their views
on real impact on service business !<o:p></o:p></span></div>
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<span style="color: #990000;"><b><u><span style="font-family: Arial, sans-serif; font-size: 10pt;">Employees:</span></u><span style="font-family: Arial, sans-serif; font-size: 10pt;"><o:p></o:p></span></b></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">During the merger acquisition process there are mostly/at-least
two group of employees evolved, coming from the organization with different
culture. In this transition phase, most of the employees faces challenges,
especially on uncertain future, career. They would also be in phase where they
think whose job is on critical edge ! This time frame is critical for employees
as they need to make sure they are synced with other culture, people, style and
way of work along with their individual performance ! Change is always
difficult for employees especially they are not engaged in decision that impact
their jobs and career. This could lead to a stress for individual and can impact
on personal growth.<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">I had a talk with couple employees who were in same situation
and got a smell that employees in this situation may fear losing their jobs or
losing opportunities they had. These type of fear can negatively impact on
productivity and eventually companies growth engine if continues. One more
important point that I realize is “conflict with competitiveness”. When
employees are in fear of losing jobs they are more likely to become competitive
with others in the same path and eventually can end up having conflict.
Competition is good if it is not creating violence !!</span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-bidi-font-size: 11.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: Wingdings; font-size: 10.0pt; mso-bidi-font-family: Arial; mso-fareast-font-family: "Times New Roman";">J</span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-bidi-font-size: 11.0pt; mso-fareast-font-family: "Times New Roman";"> </span><span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">These could be major factors where employees gets affected during
merger / acquisitions and would be happy to hear views experience from industry experts.<o:p></o:p></span></div>
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<span style="color: #222222; font-family: "Arial","sans-serif"; font-size: 10.0pt; mso-fareast-font-family: "Times New Roman";">Thanks,<o:p></o:p></span></div>
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<span style="font-family: Arial, sans-serif; font-size: 10pt;"><span style="color: #990000;">ASIC With Ankit</span></span></div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-35491604702597084922014-08-24T13:56:00.000-07:002014-08-25T13:22:58.527-07:00System Verilog Assertions (SVA) – Types, Usage, Advantages and Important Guidelines!!ASICs continue to grow in size and complexities and in this case, traditional verification techniques are not sufficient to achieve verification confidence. In the complex designs, debugging simulations is an ever increasing challenge. To address these challenges assertion based verification is found. Design and Verification engineers can place assertions in design or bind to design which will be useful to monitor, report and take action when incorrect behavior is detected. Assertions are playing major role in test bench development which helps achieving maximum confidence on bug free design. Moreover it can be used in simulations as well as in formal verification.It enables engineers to leverage the strength for block level, subsystem level and for chip level verification in order to reduce the overall effort and efficient verification closure. System Verilog Assertions are setting up a viable and effective standard in the design and verification. An assertion adds an advantage in debugging process and makes complex simulation debug easy.<br />
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Below figure on block diagram gives brief idea on where we put the assertions in test bench development. As we can see assertion are placed on module boundaries to signals to monitor DUT interface<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNvqXrHSGkZlfl4gM5xJk-4C3U5V7OL7eiIKnqsstEdDEK7GCsfs7lwq6aUmZ_PaQQchxoQEjL44bRfD3k9aPrPtIqKJUMAMYR8GiL5RFkbdNmD4NcHhs8NlDZv5hp4-NAgNu20uxSW9M/s1600/SVA_article_Image.jpg"><img border="0" height="230" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNvqXrHSGkZlfl4gM5xJk-4C3U5V7OL7eiIKnqsstEdDEK7GCsfs7lwq6aUmZ_PaQQchxoQEjL44bRfD3k9aPrPtIqKJUMAMYR8GiL5RFkbdNmD4NcHhs8NlDZv5hp4-NAgNu20uxSW9M/s1600/SVA_article_Image.jpg" width="400" /></a><br />
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The introduction of SVA added the ability to perform immediate and concurrent assertions for Design as well as for Verification. Assertions are used to validate design whether it is working correctly or not. Assertions can be useful to make sure ‘How good is the test case?’ Furthermore, it provides a means to measure the quality of the verification process through the creation of coverage using cover property feature of System Verilog assertion.<br />
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In System Verilog there are two types of assertions:<br />
<b><span style="color: #990000;"><br /></span></b>
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<div>
<b><span style="color: #990000;">Immediate Assertions</span></b><br />
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Immediate Assertion as name implies, execute immediately, in zero simulation time. It can be used in initial and always procedures, task and functions. This type of assertions performs a true/false. If the test result is true it executes the pass statement and if the test result is false or unknown, it executes false statement. Pass statements are optional; most engineers don’t prefer to specify pass statement as they are more interested on failures.<br />
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<i><span style="color: #990000;">For example:<br /><br />assert_xyx : assert (XYZ) $display (“Pass message”);<br /><br /> else $display (“Fail Message”);</span></i><br />
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<div>
<b><span style="color: #990000;">Concurrent Assertions</span></b><br />
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A concurrent assertion uses a clock to trigger the assertions evaluation. Difference between concurrent and immediate assertions is that concurrent assertions evaluate condition over time, whereas immediate assertions test at the point in time when the assertion is called. This assertions can be specified in initial block, always block or standalone like continues assignment<br />
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<i><span style="color: #990000;">For example:<br /><br />property XYZ;<br /><br /> @(posedge clk) disable iff (!rst_n)<br /><br /> ABC |=> ## [0:10] (abc == xyz);<br /><br />endproperty : XYZ<br /><br /> long_lable_p : assert property (XYZ);<br /><br />else $error (“Error : failure message”);<br /><br /> long_lable_c : cover property (XYZ);</span></i></div>
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<b><span style="color: #990000;"><br /></span></b></div>
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<b><span style="color: #990000;">Assertion Advantages</span></b></div>
<div>
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<ul>
<li>Dozens of lines of code can be represented in one line using SVA code.</li>
<li>Assertions can be controlled and can be disabled at any point during the simulations. SVA can be turned off during the reset or until the simulation reaches the particular event or logic.</li>
<li>Assertion can have severity levels, failures can be non-fatal or fatal errors.</li>
<li>SVA can be ignored by synthesis; designer does not need to include translate_on and transalate_off throughout the RTL code.</li>
<li>Assertions can be used in simulation and formal verification.</li>
<li>An assertion helps in debugging the complex failure. Debugging using end-to-end checkers requires tracing the error from the external interface back to the source. In complex designs, debugging is almost impossible without the help of intermediate checkers. As assertions pinpoint errors at the source, they can be used as intermediate checkers and debugging can be made much easier and faster.</li>
</ul>
<b><span style="color: #990000;">Who/Where should write assertions?</span></b><br />
<br />
System Verilog is nothing but an extension of Verilog;it has everything to support Verilog with lots of new features for Verification as well as for design.Usually Verification engineers add assertions to a design after the HDL models have been written which means placing the assertions on module boundaries to signals within the model, or modifying the design models to insert assertions within the code.<br />
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Design Engineers can write assertion within a design while the HDL models are being coded. What type of assertions and scenario designer should provide within design need to decide before design work begins. Verification engineer define the assertion scenario during the test bench architecture. System Verilog assertions are mostly hooked up at the DUT interface level where it can continuously check protocol and functional activities.<br />
<b><span style="color: #990000;"><br /></span></b></div>
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<b><span style="color: #990000;">Assertions controllability and why is it important?</span></b><br />
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Controllability is very important in Assertion design. There are two methods I called to control the assertions: You can also find the Assertion controlabilty blog post from "<a href="http://asicwithankit.blogspot.com/2012/04/sva-system-verilog-assertions-dynamic.html">SVA Control Method</a>" ! </div>
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<b><span style="color: #990000;"><br /></span></b></div>
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<b><span style="color: #990000;">D Method (Dynamic Method)</span></b><br />
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Dynamic method is very popular where engineers required to control the assertion dynamically based on the test scenario they wants to execute. In today’s complex SoCs and their verification, Dynamic (D) method is popular as we regress the erroneous scenario to make sure DUT behaves accordingly. In this type of simulations engineers can dynamically switch on/off assertions.<br />
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System Verilog includes system calls for controlling the execution of assertions during simulations. There are three types of D Method.<br />
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<i>1. <span style="color: #990000;">$assertoff:</span></i>This system function is used to disable all assertions but allows currently active assertions to complete before being disabled.<br />
<i>2 <span style="color: #990000;">$asserton:</span></i>This system function is used to turn all assertions back on<br />
<i>3. <span style="color: #990000;">$assertkill: </span></i>This system function used to kill and disable all assertions including currently active assertions.<br />
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By using $assertoff, the assertions specified as argument of this function will be turned off until a $asserton is executed. This way you can control assertions dynamically. Using these system tasks you can make your assertions dynamic and based on requirement we can make them enable or disable. Furthermore we can even kill using $assertkill.Dynamic control of Assertions can be used to turn off assertions during reset and initialization or during simulation erroneous protocol behavior.</div>
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<b><span style="color: #990000;"><br /></span></b></div>
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<b><span style="color: #990000;">S Method (Static Method):</span></b><br />
<br />
To control assertion statically we can use System Verilog’s pre-processing capabilities. In this method assertions are generally ignored during the compilation phase w.r.t to `ifdef. This way we can build a different model by defining a different defines. Pre-processing defines can be applied to any place of the code and thus we can control the assertion as per need.<br />
<br />
<span style="color: #990000;"><i>Example:<br /><br />`ifdef XYZ_ASSERTION_ON<br /><br /> property XYZ (@posedge awa_clk);<br /><br />a ##2 b;<br /><br />endproperty<br /><br /> XYZ_p : assert property (XYZ)<br /><br />else $fatal (“ERROR : Failed message)<br /><br /> `endif</i></span><br />
SVA proved to be a powerful assertion language; it provides several ways to control assertion. There are various reasons why assertions controllability is important, some important points are mentioned below:</div>
<div>
<ul>
<li>To turn off assertions during reset and initialization or during simulation of erroneous protocol by doing this expected fails/checks can be turned off</li>
<li>Static control of assertions is used to speed up simulations time by turning off checks or to select appropriate assertion model for a given scenarios.</li>
<li>Dynamic method gives a control on when and where to start and stop/kill the assertions. It gives powerful controllability on simulation control</li>
</ul>
<b><span style="color: #990000;">Coding Guidelines for SVA</span></b></div>
<div>
<ul>
<li>Design code shall not repeated in assertions, it will not be efficient. By making sure not repetition concept, we can decide on use of concurrent or immediate assertions for assertion check. This can be done during the architectural phase of assertions.</li>
<li>Occurrence of “X” shall be checked explicitly, because “X” is implicitly mapped to “0”, which might hide a real assertion failure.</li>
<li>Make assertions message as clear as possible. This will help in debugging the assertions.</li>
<li>Disable the assertions during resets. Concurrent and Immediate assertions in combinational logic will begin executing at the start of the simulation, before reset and during reset design might not be in the known, stable state. Hundreds of false assertions can be reported during this phase and these false assertions could hide a real failure.</li>
<li>Assertion shall use the same clock as the design; otherwise synchronization will not work properly.</li>
<li>Assertion needs to consider the reset same as the design reset. This will avoid clock cycle offset which mostly produces illegal failure.</li>
<li>Name each assertion with meaningful naming convention; this will help in debugging the failure from the failure message and from the wave form display. If we don’t provide long meaning full ‘label’ to the assertion, only non-descriptive generic name will be displayed in the waveform. By looking at the wave engineers will be unable to identify the problem until they consult the original source code. By adding the long descriptive label, we can see the label name on wave itself and can be easily identify the assertion failure details.</li>
<li>Since the long label names are visible in waveform, it is good idea to use a label naming convention for each label with “ERROR_” followed by description of what the error message is if the assertion fails.</li>
<li>Use sequence layer as much as possible because sequences can be instantiated within the sequences and properties while properties can’t be instantiated in sequences.</li>
<li>Identify implementation specific corner cases using cover properties, this will help ensure DUT is exercised properly</li>
</ul>
Note : Same article is published on Electronicsmaker.com and can be found from <a href="http://electronicsmaker.com/system-verilog-assertions-sva-types-usage-advantages-and-important-guidelines" target="_blank">here</a><br />
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Happy reading !<br />
<a href="http://www.asicwithankit.blogspot.com/">ASIC With Ankit</a></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Dear AWA Readers</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Here we go with follow up post on
‘Class – The classical feature’ ! In this post I will try to cover different
types of classes in brief for better understanding. There are various types of
classes that we use in test bench development.
The usage of class is depends on the requirements. Let’s understand what different types of classes
that we use in system verilog.</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Different types of classes:</span></div>
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<ol>
<li><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Basic Class</span></li>
<li><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Abstract Class</span></li>
<li><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Parameterised Class</span></li>
<li><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Nested Class</span></li>
<li><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Typedef Class</span></li>
</ol>
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<b><u><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Basic Class:</span></u></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Basic class is covered in my last
post, you can refer It from <a href="http://asicwithankit.blogspot.com/2013/08/class-classical-feature.html" target="_blank"><span style="color: #990000;">here</span></a>.</span></div>
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<b><u><span style="color: #990000; font-family: Arial, Helvetica, sans-serif;">Abstract Class:<o:p></o:p></span></u></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Classes without intending to
create any objects of class are called Abstract classes. These type of classes exists simply as a base
class from which other classes can be derived. Virtual class is a temple or
place holder for derived classes, abstract class is declared with a key word <span style="color: #990000;">‘<b>virtual</b>’ </span></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><span style="color: #990000;">virtual class</span></b> asic_with_ankit ;</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><span style="color: #990000;">virtual task</span></b> awa1 ();</span></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">endtask</span><o:p></o:p></span></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><span style="color: #990000;">virtual task</span></b> awa2 ();</span></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">endtask</span><o:p></o:p></span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">endclass</span><o:p></o:p></span></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Methods (tasks/functions) can be
declared virtual, if methods are declared as virtual and is overwritten in
derived class, return types, numbers and types of its arguments must be same as
of virtual method. Virtual method defined in abstract class need not have body,
In this case body will have to be defined in non virtual (non abstract) derived
class.</span></div>
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<b><u><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></u></b></div>
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<b><u><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">Parameterised class</span><o:p></o:p></span></u></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">You might be knowing the
parameterised modules in verilog/system verilog. Classes can also be
parameterised in the same way that modules are. This type of class definition
provides a template of an actual class, definition of actual class will be
created at the time of class instantiation.</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Placeholder/template for
parameterized class</span></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;"><b>class</b> </span>asic_with_ankit # (parameter int A = 1);</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"> <span style="color: #990000;"><b>bit</b>
</span>[A-1 : data];</span></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">endclass</span><o:p></o:p></span></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Actual class will be created when
you instantiate the class with parameter value</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">asic_with_ankit #(8)
awa ;</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Data type also possible to pass
as an parameter.</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;"><b>Class</b> </span>asic_with_ankit #(type
A = bit);</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"> A
register_bit;</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"> <span style="color: #990000;"><b>task</b>
</span>register_update (A reg_update);</span></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;">endclass</span><o:p></o:p></span></b></div>
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<b><u><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></u></b></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><u><span style="color: #990000;">Nested Class:</span></u></b><b><u><o:p></o:p></u></b></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Definitions appear inside the definitions of another class
as it were a member of other class. In system Verilog you are allowed to use
class within another class. Class declarations nested inside a class scope are
public and can be accessible outside of the class.<o:p></o:p></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;">Nested class helps increasing encapsulations and lead to
more readable and maintainable code.<o:p></o:p></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #990000;"><b>class</b><span class="apple-converted-space"> </span></span>A;<span class="apple-converted-space"> </span><br />
<b> <span class="apple-converted-space"> </span><span style="color: #990000;">class</span></b><span class="apple-converted-space"><span style="color: #990000;"> </span></span>B; // Nested class for a node in a
linked list.<span class="apple-converted-space"> </span><br />
<span class="apple-converted-space"> </span>bit [7:0] reg;<span class="apple-converted-space"> </span><br />
<b> <span class="apple-converted-space"> </span><span style="color: #990000;">endclass</span></b><span class="apple-converted-space"><span style="color: #990000;"> </span></span><br />
<span style="color: #990000;"><b>endclass</b><span class="apple-converted-space"> </span></span><o:p></o:p></span></div>
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<span style="color: #990000; font-family: Arial, Helvetica, sans-serif;"><b><u>Typedef Class</u></b><b><u><o:p></o:p></u></b></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;">Sometimes a class
variable needs to be declared before the class itself has been declared.<o:p></o:p></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;">For example,<o:p></o:p></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><span style="color: #990000;">typedef class</span></b>
ASIC_With_Ankit;<o:p></o:p></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"> <span class="apple-converted-space"> </span><span style="color: #990000;"><b>class</b><span class="apple-converted-space"> </span> </span>AWA;<o:p></o:p></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"> <span class="apple-converted-space"> </span>ASIC_With_Ankit <span class="apple-converted-space"> </span>AWA1;<o:p></o:p></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b> <span class="apple-converted-space"> </span><span style="color: #990000;">endclass</span></b><b><o:p></o:p></b></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;">“typedef class
ASIC_With_Ankit;” <span class="apple-converted-space"> </span>: typedef
of class ASIC_With_Ankit allows compiler to process the class before it uses
inside the class<span class="apple-converted-space"> </span> AWA. This
will avoid the compilation error otherwise <span class="apple-converted-space"> </span>compiler will flag an error.<span style="color: #222222;"><o:p></o:p></span></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;">Hope this will be useful information on understanding of different classes in system verilog and their usage.</span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></div>
<div style="background-color: white;">
<span style="font-family: Arial, Helvetica, sans-serif;">Happy reading ! </span></div>
<div style="background-color: white;">
<span style="color: #990000; font-family: Arial, Helvetica, sans-serif;"><a href="http://asicwithankit.blogspot.com/" target="_blank">ASIC With Ankit</a></span></div>
</div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-17201806123071470202013-08-24T20:27:00.000-07:002014-04-12T14:37:52.137-07:00"Class" - The Classical feature - Part I<div class="separator" style="clear: both; text-align: center;">
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Dear Readers,<br />
<br />
Let's understand the classical feature of System Verilog '<b><span style="color: #660000;">Class</span></b>'. Here I would try to explain on class feature, object properties and methods, object instantiation, class methods polymorphism and constructor concept.<br />
<br />
What is class and why is it classical :), Lets understand<br />
<ul>
<li>Class is a generalization of the data type concept and central to the Object Oriented Programming. </li>
<li>A class is a type that includes data and subroutines like functions and tasks. </li>
<li>The class properties and methods creates a capabilities of some kind of objects.</li>
</ul>
<div>
Usage of class with example:</div>
<div>
<br /></div>
<div>
<i><span style="color: #660000;"><b>class</b> AsicWithAnkit ;</span></i></div>
<div>
<i><span style="color: #660000;">//Data of class properties</span></i></div>
<div>
<i><span style="color: #660000;"> <b>bit</b> [3:0] cmd ;</span></i></div>
<div>
<i><span style="color: #660000;"> <b>bit</b> [7:0] addr;</span></i></div>
<div>
<i><span style="color: #660000;"> <b>int</b> count;</span></i></div>
<div>
<i><span style="color: #660000;"> <b>bit</b> ack;</span></i></div>
<div>
<i><span style="color: #660000;"><br /></span></i></div>
<div>
<i><span style="color: #660000;"> //Initialization</span></i></div>
<div>
<i><span style="color: #660000;"> <b>function new</b> ();</span></i></div>
<div>
<i><span style="color: #660000;"> cmd = 3'b000;</span></i></div>
<div>
<i><span style="color: #660000;"> addr = 8'h00;</span></i></div>
<div>
<i><span style="color: #660000;"> <b>endfunction</b></span></i></div>
<div>
<i><span style="color: #660000;"><br /></span></i></div>
<div>
<i><span style="color: #660000;"> //Methods</span></i></div>
<div>
<i><span style="color: #660000;"> <b>function</b> display ();</span></i></div>
<div>
<i><span style="color: #660000;"> $display ("Command =%h", cmd );</span></i></div>
<div>
<i><span style="color: #660000;"> $display ("Addresss =%h," addr); </span></i></div>
<div>
<i><span style="color: #660000;"> <b>endfunction</b> : display</span></i></div>
<div>
<i><span style="color: #660000;"><br /></span></i></div>
<div>
<i><span style="color: #660000;"> <b>task</b> clean ();</span></i></div>
<div>
<i><span style="color: #660000;"> cmd = 'h0;</span></i></div>
<div>
<i><span style="color: #660000;"> addr = 'h0;</span></i></div>
<div>
<i><span style="color: #660000;"> <b>endtask</b> : clean</span></i></div>
<div>
<i><span style="color: #660000;"><br /></span></i></div>
<div>
<i><span style="color: #660000;"><b>endclass</b> : AsicWithAnkit</span></i></div>
<div>
<br /></div>
<div>
Above example gives an idea on how to declare a class and their properties, usage of those properties by instantiating class object is the next step to use properties defined inside class body.</div>
<div>
<br /></div>
<div>
Lets understand how to instantiate class object, we will have to create a memory for class object to use class properties and their methods for further development work.</div>
<div>
<br /></div>
<div>
<span style="color: #660000;"><i>AsicWithAnkit AwA;</i></span></div>
<div>
<span style="color: #660000;"><i>AwA = <b>new </b>;</i></span></div>
<div>
<br /></div>
<div>
Here we can see class name "AsicWithAnkit" is instantiated with a created ovject name "AwA". in second statement we are creating a memory for class object "AwA". Now we are ready to use class properties using instantiated object. Let's understand how?</div>
<div>
<br /></div>
<div>
Now when you want to access or use the properties described in the class you can use/access those methods using the objects.<br />
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<i><span style="color: #660000;">AsicWithAnkit AwA = <b>new </b>;</span></i><br />
<i><span style="color: #660000;">AwA.cmd = 'h2 ;</span></i><br />
<i><span style="color: #660000;">AwA.addr = 'h8 ; //Accessing a class properties using object</span></i><br />
<i><span style="color: #660000;">AwA.display (); //Accessing a class method using object</span></i><br />
<br />
This way we can access class variables and methods using instantiated objects. System verilog does not require memory allocation and deallocation.<br />
<br />
System verilog gives us a different option/way through which we can assign, re-name and copy the objects.<br />
Class has many system verilog features and will try to cover those feature in separate follow up blog posts.<br />
<br />
<span style="font-size: x-small;">Note : Same blog has been published on EDACafe and is available from <span style="color: #990000;"><a href="http://www10.edacafe.com/blogs/asicwithankit/2013/10/31/class-the-classical-feature/" target="_blank">here</a></span></span><br />
<br />
Keep Reading....<br />
<a href="http://www.asicwithankit.blogspot.com/" target="_blank">ASIC With Ankit</a></div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com5tag:blogger.com,1999:blog-2924155476004584973.post-10964941083108626162013-05-27T00:07:00.001-07:002013-05-27T00:07:10.382-07:00What is "this" in System Verilog ?Dear Readers,<br />
<br />
Here I would like to share some understanding on keyword called <b>"this"</b>. What is <b>"this"</b> in System Verilog? How does it used? Usage of <b>"this"</b> is simple but important in test bench development.<br />
<br />
First of all lets understand What is <b>"this"</b> in System Verilog?<br />
<br />
<b>"this" </b>is a key word in System Verilog used to unambiguously refer to class properties or methods of current object. The <b>"this" </b>keyword shall only used within a non-static class methods otherwise an error shall occur.<br />
<br />
As example is the best way to understand the most of the things, let me take a example and try to explain.<br />
Example to understand the usage of <b>"this" </b>in System Verilog:<br />
<br />
<span style="color: #990000;">#############################################</span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;"><i> <b>class</b> ASICwithAnkit ;</i></span><br />
<span style="color: #990000;"><i> <b>int</b> a ;</i></span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;"><i> <b>function new</b> (<b>int</b> a);</i></span><br />
<span style="color: #990000;"><i> <b>this</b>.a = a;</i></span><br />
<span style="color: #990000;"><i> <b>endfunction</b> : new</i></span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;"><i> <b>endclass</b> : ASICwithAnkit</i></span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;"><i>//Class instantiation and usage</i></span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;"><i>ASICwithAnkit AwA = <b>new</b> (123);</i></span><br />
<span style="color: #990000;"><i><b>$display</b> ("AwA.a = %d,", AwA.a);</i></span><br />
<span style="color: #990000;"><i><br /></i></span>
<span style="color: #990000;">##########################################</span><br />
<br />
In above example we can see that 'a' is a member of class "ASICwithAnkit". When we initialize the memory for class for usage, we have passed a integer value '123' to its constructor (function new). The variable 'a' is local to class instance "AwA and is now 123 as we have passed this from constructor.<br />
<br />
Hope this is useful to understand the meaning and usage of <b>"this" </b>in System Verilog.<br />
<br />
<span style="font-size: x-small;">Note : Same blog is available on <a href="http://forum.eetindia.co.in/BLOG_ARTICLE_17203.HTM" target="_blank">EETimes India</a> site.</span><br />
<br />
Happy Reading !<br />
<a href="http://www.asicwithankit.blogspot.com/" target="_blank">ASIC With Ankit</a>Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com0tag:blogger.com,1999:blog-2924155476004584973.post-12175483893604040502013-05-17T23:16:00.000-07:002013-05-27T00:14:01.091-07:00System Verilog Queues which can shrink and grow !Dear Readers,<br />
<br />
System Verilog has new data type called ‘queue’ which can
grow and shrink. With SV queue, we can easily add and remove elements
anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In First Out) type of buffers.<br />
<br />
Each element in the queue is identified by an ordinal number that represents its position within the queue, with 0 representing the first element and $ represents the last element.<br />
<br />
The size of the queue is variable similar to dynamic array but queue may be empty with zero element and still its a valid data structure.<br />
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<div class="MsoNormal">
Lets take a few examples to understand queue operation with
different methods we have in system verilog.<o:p></o:p></div>
<div class="MsoNormal">
<o:p><br /></o:p></div>
<div class="MsoNormal">
<o:p><span style="color: #990000;">############################################### </span></o:p></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><b>int</b> a;<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;">Q[$] = {0,1,2,3}; //
Initial queue<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><br /></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><b>initial begin</b><o:p></o:p></span></i></div>
<div class="MsoNormal">
<span style="color: #990000;"><b> //</b><b style="font-style: italic;">Insert and delete</b><i><o:p></o:p></i></span></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> Q.insert (1, 1); // This means insert 1 at first element in
the queue which becomes {0,1,1,2,3}<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> Q.delete(2); // This means delete 2<sup>nd</sup> element
from the queue. {0,1,2,3}<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><br /></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> <b>//Push_front</b><o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> Q.push_front (6); //Insert
‘6’ at front of the queue. {6,0,1,2,3}<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><br /></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> <b>//Pop_back</b><o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> a = Q.pop_back; //
Poping the last element and stored it to local variable ‘a’, a = 3 in this case. Resultant Queue = {6,0,1,2}<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><br /></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> <b>//push_back</b><o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> Q.push_back(7) // Pushing the element ‘7’ from the back. {6,0,1,2,7}<o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> </span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> <b>//Pop_front:</b><o:p></o:p></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"> a =Q.pop_front; Poping the first element and stored it to
local variable called ‘a’, a=6 in this case. Resultant Queue = {0,1,2,7}</span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><br /></span></i></div>
<div class="MsoNormal">
<i><span style="color: #990000;"><b>end</b></span></i></div>
<div class="MsoNormal">
<o:p><span style="color: #990000;">##################################################### </span></o:p></div>
<div class="MsoNormal">
<o:p><br /></o:p></div>
<div class="MsoNormal">
When you create a queue System Verilog actually allocates extra space and because this we can add and remove the element based on need in our test bench. This is very useful feature in test bench implementation. System Verilog automatically allocates the additional space so we don't need to worry about the limits and queue will not run out of space.<o:p></o:p></div>
<div class="MsoNormal">
<br /></div>
<div class="MsoNormal">
Queue is very useful data type in System Verilog for developing a test benches. It can be used in development of various entity in the test bench like scoreboard, monitor, transaction class, drivers etc.</div>
<div class="MsoNormal">
<br /></div>
<div class="MsoNormal">
Hope this helps in basic understanding of queue and its methods.</div>
<div class="MsoNormal">
<br />
<span style="font-size: x-small;">Note : Same blog article is also available on <a href="http://www10.edacafe.com/blogs/asicwithankit/2013/05/18/system-verilog-queues-which-can-shrink-and-grow/" target="_blank">EDA Cafe</a> website.</span><br />
<br /></div>
<div class="MsoNormal">
Happy Reading!</div>
<div class="MsoNormal">
<a href="http://www.asicwithankit.blogspot.com/" target="_blank">ASIC With Ankit</a> </div>
Ankit Gopanihttp://www.blogger.com/profile/15162516749057715307noreply@blogger.com2