What is "this" in System Verilog ?

Dear Readers,

Here I would like to share some understanding on keyword called "this". What is "this" in System Verilog? How does it used? Usage of "this" is simple but important in test bench development.

First of all lets understand What is "this" in System Verilog?

"this" is a key word in System Verilog used to unambiguously refer to class properties or methods of current object. The "this" keyword shall only used within a non-static class methods otherwise an error shall occur.

As example is the best way to understand the most of the things, let me take a example and try to explain.
Example to understand the usage of "this" in System Verilog:

#############################################

     class ASICwithAnkit ;
        int a ;

        function new (int a);
           this.a = a;
        endfunction : new

     endclass : ASICwithAnkit

//Class instantiation and usage

ASICwithAnkit  AwA = new (123);
$display ("AwA.a = %d,", AwA.a);

##########################################

In above example we can see that 'a' is a member of class "ASICwithAnkit". When we initialize the memory for class for usage, we have passed a integer value '123' to its constructor (function new). The variable 'a' is local to class instance "AwA and is now 123 as we have passed this from constructor.

Hope this is useful to understand the meaning and usage of "this" in System Verilog.

Note : Same blog is available on EETimes India site.

Happy Reading !
ASIC With Ankit