Sunday, December 16, 2012

System Verilog : Functional Coverage Options features

Dear Readers,

Functional Coverage is very important in Test Bench Design. It gives us a confidence on covered items listed on verification plan/items. Usually the goal of verification engineer is to ensure that the design behaves correctly in its real environment.

Defining coverage model is very important for any test bench to get the enough confidence on design verification. You can read more on 'Coverage Model in System Verilog'

Here I would like to share some of the important feature of System Verilog Functional Coverage which helps engineer during verification activity.

Coverage Options available in System Verilog through which you can specify additional information in the cover group using provided options

1. Cover Group Comment - 'option.comment'
You can add a comment in to coverage report to make them easier while analysing:

covergroup CoverComment ;
  option.comment = "Register Definition section 1.1";
  coverpoint reg;

In example, you could see the usage of 'option.comment' feature. This way you can make the coverage group easier for the analysis.

2. Per Instance Coverage - 'option.per_instance'
In your test bench, you might have instantiated coverage group multiple times. By default System Verilog collects all the coverage data from all the instances. You might have more than one generator and they might generate different streams of transaction. In this case you may want to see separate reports. Using this option you can keep track of coverage for each instance.

covergroup CoverPerInstance ;
  coverpoint tr.byte_cnt;
  option.per_instance = 1;

3. Threshold using - 'option.at_least' 
This feature is useful when you don't have sufficient visibility in to the design to gather robust coverage. There might be the cases where you just have an information of number of cycles that are needed for the transfers to cover required errors to get generated/simulated for defined cover point. Here you could set the option.at_leaset. For example if we know that we need 10 cycles to cover this particular cover point, you could define option.at_leaset = 10.

4. Control on Empty bins - option.cross_num_print_missing = 1000
System verilog coverage report by default shows only the bins with samples. But usually as a verification engineer our job is to verify all cover point that are listed in verification plan.

covergroup CoverCrossNumPrintMissing ;
    ByteCnt : coverpoint tr.byte_cnt;
    Length : coverpoint tr.length;
   option.cross_num_print_missing = 1000;

5. Coverage Goal - option.goal
In system verilog, coverage goal for a cover group or point is the level at which the group or point is considered fully covered.

covergroup CoverGoal ;
    coverpoint tr.length;
    option.goal = 80;

These are the few important coverage option features which are very useful in defining/coding System Verilog Functional Coverage.

Keep Reading,
ASIC With Ankit


Putta Satish said...

option.auto_bin_max is missing in this listing

Ankit Gopani said...

Hi Putta Satish,

Thanks for reading the blog posts.
Yes, it is missing in this list. Idea was to capture few of items to explain how it is useful in coverage model implementation.

You can still find the all supported list in coverage from System Verilog LRM, chapter 20, table 20-1, 20-2.

Keep reading.

Santosh Matagar said...

Here my doubt is regarding coverage bin.
e.g. coverpoint cp {
bins x =0;
bins y =1; }
my project is having multiple variations, x & y both are not valid for all variations. so with which option i can control this, please let me know.

Ankit Gopani said...

Hi Santosh,

Well in system Verilog you have illegal_bins and ignore bins constructs. You can use either one, both has their importance and significance, please see the usage from this blog post.

Hope this will be useful or let me know if you have further questions on the same.