Plus args in System Verilog is Plus point !!

Dear Readers,

'Plus args in System Verilog is Plus point !!' Statement itself says that here I am going to share on some plus points and how to control Plus args in very popular design verification language called System Verilog (SV).

Plus args are command line switches supported by the simulators. Usually they are application specific. As per System Verilog LRM arguments beginning with the '+' character will be available using the $test$plusargs and $value$plusargs PLI APIs. Plus args are very useful in controlling many things on your environment like controlling your debug mode or to set a value like the debug_level in your environment, set a value to select/deselect particular field in your environment in your simulation.

What is the Syntax :
$value$plusargs (string, variable)

This is a system function searches the list of plusargs. For this system in build function, If a string is found the function returns the value 1'b1. If no strong is found matching, the function returns the value 1'b0 and the variable provided is not modified.

Let's take an example, How should we use this functions in our environment to have control.

begin
bit erro_injection;
error_injection = 0;
if ($test$plusargs ("err"))
error_injection = 1;
$display ("Error Injection =$d", error_injection);
end

begin
  if ($value$plusargs ("TESTNAME=%S", testname))
  begin
    $display ("Running test  %0s.", testname);
    starttest();
  end
end

Usage:
'Simulator Command' : +err +TESTNAME=this_test

Here in example, we could see how can we use the $test$plusargs System in build function to have control over error injection as well to select the test case name. This is just an example you can implement your own different arguments based on your application and requirement on various functionality. You can use these different arguments to pass from command line arguments like to get clock, frequency, test name, error injection information from command line.

These kind of switches are very helpful for user to control the environment without knowing the functionality. For example if user wants to run/simulate particular test case with selected frequency and clock information with debug mode enable and error injection disable, he/she just have to pass the appropriate arguments/switches from command line as we discussed in above example.

Here Engineers needs to well take care the implementation logic to give these kind of controlibility for user. He/She has to think in advance on what kind of control we can provide to user to make their life peaceful ! Once we have detailed information on what controls we need to give user, we can implement our environments to support those all switches/arguments in our environment using system in build functions.

This way we can have control over environment using plusarg feature, this is a plus point in Verilog as well as in System Verilog and because of these I would say "Plus args in these languages are Plus Point"

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