How to Randomize non-random variable in System Verilog


System Verilog is industry adopted very popular hardware descriptive language, most of the companies in industry have been using this language for complex SOC, ASIC design and verification.

System verilog has various ways you can randomize values and fields to generate random stimulus for complex system verification. Randomizing variables and fields which are declared as rand are easy to randomize with or without constraints. In system verilog you can just do object.randomize() and all variables and fields declared as rand will gets random values during the simulation. 

There could be different situation where one require to know how to generate random values for variables which are not declared as rand? The answer is scope randomize function (std::randomize())

std::randomize() is a scope randomize function that enables users to randomize data in the current scope. This method is also very useful if some variables required to be randomized are not part of a class. 

Lets understand this with simple example:

module my_module;

  bit [15:0] address;

  bit [31:0] data;

  function bit my_test ();

    bit pass;

    bit read_write;

    pass = std::randomize(address, data, read_write);

    return read_write;

  endfunction

endmodule

In this example, if you notice, we are using all these variables for scope randomize function. When you run this type of code usage, it std::randomize function will randomize all variables in its scope to generate random values without needing to use .randomize() method.

Now that we learn to randomize variable which are not rand in nature, you might have question what about constraints? How should we write constraints in this method. Good news is, you can. You can provide your constrains using "with" something like below:

pass = std::randomize(address, data, read_write) with {read_write -> address > 'h000F ;};

Hope you find this information useful. Stay tuned for more interesting stuffs about verification!

-ASIC With Ankit