Sunday, March 17, 2013

System Verilog : Which final is Final ?

Dear Reader,

Recently I posted one blog post “System Verilog Final Means Final !”

As we all know final means final in system Verilog, Final block will get called at the end of the simulation before $finish. Now with this understanding we can have few questions. Recently I have received an request and some question on the same like and thought of answering those questions.
  1. Is multiple final block is allowed in System Verilog?
  2. If yes, what will be the execution order in simulation, which final is final?
Here are the answers to these questions :

Multiple final blocks are allowed in system Verilog, you can define multiple final block in your testbench. Some time you might require to use final blocks in different places of environment. Here we need to understand one most important thing on final block is that, final blocks are called at the end of the simulation before $finish. It is like a calling a function which executes in zero simulation time.

If you have multiple final block in your testbench all final blocks are called at same simulation time before your simulation ends. Let’s take an example to have better understanding:

program ankit_with_ankit;

  class final_test;
     task final_activity();
        $display (“ASIC With Ankit 1 @%t”,$time);
         #10;
       $display (“ASIC With Ankit 2 @%t”,$time);
     endtask
  endclass

  initial begin
     final_test ft;
     ft = new;
     ft.final_activity();
  end

  final begin
     $display (“ASIC With Ankit 3 @%t”,$time);
  end

  final begin
     $display (“ASIC With Ankit 4 @%t”,$time);
  end

endprogram

Simulation Result:

ASIC With Ankit 1 @ 0
ASIC With Ankit 2 @ 10
ASIC With Ankit 3 @ 10
ASIC With Ankit 4 @ 10

Here you can observe that I have used 2 final blocks in this simple exercises. You can have less or more based on your testbench requirement. When you run this with any simulator result will tell you all the final blocks will be called at same simulation time. So you could see all the messages for final blocks will be print at same simulation time. This is the reason you could see printing time for all the messages defined in the final blocks are 10ns.

So answer to question ‘which final is final?’ is ‘All finals are final’!

I hope this will give you a more understanding on final block usage and execution. Comments, suggestions are welcome. This blog post was published in the EDA Cafe .

Happy Reading!
ASIC With Ankit

6 comments:

Prabha Bhaktharam said...

Ankit,

I see only 2 final blocks, how is it 4?

Please explain.

Thx,
Prabha

Ankit Gopani said...

Prabha,

Good Catch! It is a typo, already corrected !

Earlier I created the same example with 4 final blocks and missed out in one of my update.

Keep reading and stay connected.

Regards,
Ankit

Hash said...

Hi Ankit

Can you also write on fork-disable?

-Regards
Subhash

Ankit Gopani said...

Hey Subhash,

Nice to see your comment.

Well, Last year, April, I wrote one blog on "System Verilog Fork Join : The most important and very useful process control feature!"

You can access this blog post from below given link:
http://asicwithankit.blogspot.in/2012/04/system-verilog-fork-join-most-important.html

In this blog post I have tried to capture process control with in build method for process disctruction. You can see point 1,2 and 3 in Process Distruction bullet.

Hope thing post will hel you to understand disable logic for fork join.

Thanks,
Ankit

POWER BOY said...

Hi Ankit,

I remember that some where that there can be only one final in a program or module and not multiple finals same as initial blocks.

Can you please correct me in this aspect.

Thanks,
SP

Ankit Gopani said...

Multiple final blocks are allowed in program block, you can refer my blog post from http://asicwithankit.blogspot.com/2013/03/system-verilog-which-final-is-final.html.

Keep reading!

Thanks,
Ankit