Dear Readers,
I have been hearing on re-spins of chips. Many companies have
gone through this painful phase because of several reason/defects. Nobody
likes re-spin for chip as it is expensive and time consuming! Companies have a
fear to loose time to market for their products because of this reason.
Let us understand the various factors which could cause
re-spin for chips. If you ask industry experts or Semiconductor veterans they could
share their experience. I have been discussing this topic with couple of people
and have concluded few factors which could cause re-spin.
- Firmware Issues
- Power Issues
- Mixed-Signal Interface related Issues
- Race Condition Issues
- Clocking domain Issues
- Functional Issue etc...
From the experience and discussion it looks like most of the
time Function Issues/defects have triggered a re-spin for the Chips. When we
talk about functional issues, attention comes to our mind is for functional logic
verification part. Considering complexities in the ASICs companies have started
investing time and money for the functional verification part of the Chips to
reduce the chances of re-spin.
To reduce the chances of re-spin for chips, people have
started using various precautions like
-
A reusable and scalable verification
-
More effective block (IP) level verification
-
Verification reuse from block level to System
level
-
Architecture of test bench using reusable
methodologies
Random functional verification is giving us a enough confidence on functional defects. Random verification generates corner scenarios, stress testing on functional scenarios and logical permutation for configuration.
Random verification just gives us a confidence on functional defects but not giving us confirmation that Chip will not have to go through re-spin because of any of the functional issue.
Share your experience on Chip re-spin.
Happy Reading-Sharing,
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