Dear Readers,
In year of 2002, this was called as OVA (Open Vera Assertions). Later on Synopsys Inc had donated the Open VERA language to the Accellera committee to be part of System Verilog language. Several other companies made contributions for the formation of the new Systerm Verolog language. System Verilog language included the assertion language as part of the standard which is called as a “System Verilog Assertions” (SVA).
For verification engineers, main objective is “to verify the design under test (DUT)” thoroughly and make sure there are no functional bugs.
I have seen different approaches to develop test bench:
1. Directed way of writing a test bench
2. Constrained random test bench
3. Semi randomize way of writing test bench
Main points while architecting any verification environments are given below:
- Simulation Generation
- Protocol Checking
- Data Checking
- Protocol Coverage
- Test Plan Coverage
If you see the history and figure it out, you could see, most of the Test benches which were developed before SVA were taking care of all above given categories. Later on when SVA introduced in System Verilog language and two categories, first Protocol Checking, second Protocol Coverage addressed by SVA. These two categories are closer to the design signals and can be managed more efficiently within SVA than by the testbench.
By connecting these assertions directly to the design, the performance of the simulation environment increases tremendously as does the productivity. Using this approach we can share information dynamically during the simulation.
We can not say that without SVA protocol and test plan coverage is not doable. People were doing those things when SVA was not invented!! I can say those parts are easy and effective using the SVA because of its strong constructs and features. For more details on coverage model and brief on Assertion please refer http://asicwithankit.blogspot.com/2011/01/coverage-model-in-system-verilog-test.html
References : A practical guide for system Verilog assertions, By Srikanth Vijayaraghavan, Meyyappan Ramanathan
Enjoy!
ASIC With Ankit
In year of 2002, this was called as OVA (Open Vera Assertions). Later on Synopsys Inc had donated the Open VERA language to the Accellera committee to be part of System Verilog language. Several other companies made contributions for the formation of the new Systerm Verolog language. System Verilog language included the assertion language as part of the standard which is called as a “System Verilog Assertions” (SVA).
For verification engineers, main objective is “to verify the design under test (DUT)” thoroughly and make sure there are no functional bugs.
I have seen different approaches to develop test bench:
1. Directed way of writing a test bench
2. Constrained random test bench
3. Semi randomize way of writing test bench
Main points while architecting any verification environments are given below:
- Simulation Generation
- Protocol Checking
- Data Checking
- Protocol Coverage
- Test Plan Coverage
If you see the history and figure it out, you could see, most of the Test benches which were developed before SVA were taking care of all above given categories. Later on when SVA introduced in System Verilog language and two categories, first Protocol Checking, second Protocol Coverage addressed by SVA. These two categories are closer to the design signals and can be managed more efficiently within SVA than by the testbench.
By connecting these assertions directly to the design, the performance of the simulation environment increases tremendously as does the productivity. Using this approach we can share information dynamically during the simulation.
We can not say that without SVA protocol and test plan coverage is not doable. People were doing those things when SVA was not invented!! I can say those parts are easy and effective using the SVA because of its strong constructs and features. For more details on coverage model and brief on Assertion please refer http://asicwithankit.blogspot.com/2011/01/coverage-model-in-system-verilog-test.html
References : A practical guide for system Verilog assertions, By Srikanth Vijayaraghavan, Meyyappan Ramanathan
Enjoy!
ASIC With Ankit
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