Dear ChipMates,
Here I came across interesting exercises with fork join, I was using fork join thread in my complex verification environment where I was playing with so many fork join threads. I was having child forks inside parent forks.
System Verilog has a strong construct called 'disable fork' through which engineer can control the fork processes. SV has three different fork processes, 1. fork-join 2. fork-join_none 3. fork-join_any. From which fork-join_none and fork-join_any needs process control because normal fork-join will comes out only when all the processes will be executed and done. But join_any will comes out when any of the process will finish its job. These places some times we need process control and we may need to disable fork thread once perticular process is done.
I have made simple exercises (given below) which will give you idea how to control fork-join with disable fork construct in System Verilog.
program test ;
class A ;
task fork_join ();
int temp = 1;
fork
begin
fork
begin
if (temp == 1)
$display ("Inside first Begin...end thread \n");
end
begin
# 100ns;
$display ("Inside second Begin...end therad\n");
end
join_any
disable fork; // This will disable only child fork
end
begin
# 50ns;
$display ("Inside Second thread of main fork \n");
end
join
endtask
endclass
initial
begin
A aa = new ;
aa.fork_join();
end
endprogram
From the above given will pring below given messages :
OUTPUT:
Inside first Begin...end thread
Inside Second thread of main fork
From the messages it seems, it has disabled the child fork proecess not the mail fork process, and as a result we are able to see second message called "Inside Second thread of mail fork"
Hope this was a useful sharing for all.
Happy Reading,
ASIC with Ankit
Here I came across interesting exercises with fork join, I was using fork join thread in my complex verification environment where I was playing with so many fork join threads. I was having child forks inside parent forks.
System Verilog has a strong construct called 'disable fork' through which engineer can control the fork processes. SV has three different fork processes, 1. fork-join 2. fork-join_none 3. fork-join_any. From which fork-join_none and fork-join_any needs process control because normal fork-join will comes out only when all the processes will be executed and done. But join_any will comes out when any of the process will finish its job. These places some times we need process control and we may need to disable fork thread once perticular process is done.
I have made simple exercises (given below) which will give you idea how to control fork-join with disable fork construct in System Verilog.
program test ;
class A ;
task fork_join ();
int temp = 1;
fork
begin
fork
begin
if (temp == 1)
$display ("Inside first Begin...end thread \n");
end
begin
# 100ns;
$display ("Inside second Begin...end therad\n");
end
join_any
disable fork; // This will disable only child fork
end
begin
# 50ns;
$display ("Inside Second thread of main fork \n");
end
join
endtask
endclass
initial
begin
A aa = new ;
aa.fork_join();
end
endprogram
From the above given will pring below given messages :
OUTPUT:
Inside first Begin...end thread
Inside Second thread of main fork
From the messages it seems, it has disabled the child fork proecess not the mail fork process, and as a result we are able to see second message called "Inside Second thread of mail fork"
Hope this was a useful sharing for all.
Happy Reading,
ASIC with Ankit
5 comments:
Ankit- Is below code race condition or not.
fork
a=1;
a=0;
join
try to chnage the order inside the fork and see what you get at output
(As per theory this is race and you dont know what will be the output here,but practically it is not a race,Check it on two different tools)
Hi Jigar,
Nice to see your comments and this is really nice question you asked.
As per my experience it depends on tools you used, but yes it would not be race condition with vcs. I have used it one of my project and with vcs it will take the value you assinged last. So in your case it will print a=0 with vcs.
Regards,
ASIC with Ankit
Ankit - "As per my experience it depends on tools you used, but yes it would not be race condition with vcs."
Jigar :
1> Race condition exist when same piece of code run on different simulation tool gives different result.
This is because Tools have to follow verilog LRM and event scheduling mechanism.
So same code when run on different simulation gives different results because of the way tool has implemented algorithms.
Order is always deterministic within one tool (If we follow there algorithm than we should get same result)
So in order to check race - you need to use two tools
Conclusion: We can not mention “It would not be a race with VCS" Rather " This is not a race as VCS/Questa is giving same result (I am assuming all other tool is behaving same ,if not than this can be considered race)
Code :
module test();
reg a;
reg b;
initial
begin
fork
a=0;
b=1;
a=1;
b=0;
join
end
initial
begin
#5
$display ("@ %t Value of a is = %b",$time,a);
$display ("@ %t Value of b is = %b",$time,b);
#100;
$finish;
end
endmodule
Result :
# run -all
# @ 5 Value of a is = 1
# @ 5 Value of b is = 0
Just adding one more point :
As of now all tools seems beahave in same menor (but if tehre is a tool which gives a=0 and b =1 than my statement will be wrong and it is a race condition theoritically as well as practically)
Or if Gopani comes with his own businees venture and develops a new tool that gives a=0, and b=1 than again it will be race condition theoritically as well as practically.
Well said Jigar,
There is no chance that I can come up with venture and launch my new tool at least for couple of years.
You are correct Jigar, all tools will behave same and it will give a=1 and b=0.
-Ankit
ASIC with Ankit
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