PASS and FAIL Messages with Colors...!

How many among you know that you can actually display color messages using Verilog and SystemVerilog?

You can implement a logic in your testbench to have nicely colored display messages at the end of your simulation which will give you a PASS/FAIL messages. I have written a piece of code given below and you can refer the same. I have captured a snapshot of output which you can see at the top.

program clr_display();
class color ;
task display ();
$write("%c[1;34m",27);
$display("***************************************");
$display("*********** TEST CASE PASS ************");
$display("***************************************");
$write("%c[0m",27);

$display("%c[1;31m",27);
$display("***************************************");
$display("*********** TEST CASE FAIL ************");
$display("***************************************");
$display("%c[0m",27);
endtask
endclass

initial begin
color clr;
clr = new ();
clr.display ();
end
endprogram

With an above example you can have a display messages with colors. So this way you can have nicely and colored messages on your terminal.

Enjoy...!
-ASIC with Ankit