Dear Readers,
Is it really possible to develop relatively complex functional coverage model using SVA (System Verilog Assertions)??
Yes, SystemVerilog Assertions (SVA) can be used to implement relatively complex functional coverage models under appropriate circumstances:
I would say using strong construct of SVA we can develop a functional coverage model too. The point here is using SVA construct you need to do some work around while in functional coverage there are some constructs using which we can simply write a cover points to cover the functionality.
Let me take an example and try to explain:
Let say we have a verification scenario where we have to cover state transitions.
It should cover
1. states transition A-B and
2. State transition B-C
This can be covered using functional coverage construct “=>” like A=>B and B=>C so basically code would be given below in functional coverage model:
covergroup state_trans_cg @ (posedge clk);
coverpoint state_trans_cov
{
bins A_to_B = (A => B);
bins B_to_C = (B => C);
}
endgroup
Same functionality we can cover using SVA constructs as well:
If we try to cover the same functionality using SVA then code would be:
sequence seq_A_B;
@(posedge clk)
`A ##1`B;
endsequence : seq_A_B
sequence seq_B_C;
@(posedge clk)
`B ##1`C;
endsequence : seq_B_C
trans_A_B : cover property (seq_A_B);
trans_B_C : cover property (seq_B_C);
In this case cover property will cover state transitions which we are covering using transition bin in functional coverage.
Like these there are lot many constructs are there in System Verilog Assertions using which we can cover functionality.
As per my knowledge and experience if you use SVA for your functional coverage then you need to play a little bit with SVA constructs while things would be easy if you use functional coverage instead.
Big Advantage to use SVA Coverage model is, Engineer does not required object oriented programming language knowledge :-)
Happy Reading,
ASIC with Ankit
Is it really possible to develop relatively complex functional coverage model using SVA (System Verilog Assertions)??
Yes, SystemVerilog Assertions (SVA) can be used to implement relatively complex functional coverage models under appropriate circumstances:
I would say using strong construct of SVA we can develop a functional coverage model too. The point here is using SVA construct you need to do some work around while in functional coverage there are some constructs using which we can simply write a cover points to cover the functionality.
Let me take an example and try to explain:
Let say we have a verification scenario where we have to cover state transitions.
It should cover
1. states transition A-B and
2. State transition B-C
This can be covered using functional coverage construct “=>” like A=>B and B=>C so basically code would be given below in functional coverage model:
covergroup state_trans_cg @ (posedge clk);
coverpoint state_trans_cov
{
bins A_to_B = (A => B);
bins B_to_C = (B => C);
}
endgroup
Same functionality we can cover using SVA constructs as well:
If we try to cover the same functionality using SVA then code would be:
sequence seq_A_B;
@(posedge clk)
`A ##1`B;
endsequence : seq_A_B
sequence seq_B_C;
@(posedge clk)
`B ##1`C;
endsequence : seq_B_C
trans_A_B : cover property (seq_A_B);
trans_B_C : cover property (seq_B_C);
In this case cover property will cover state transitions which we are covering using transition bin in functional coverage.
Like these there are lot many constructs are there in System Verilog Assertions using which we can cover functionality.
As per my knowledge and experience if you use SVA for your functional coverage then you need to play a little bit with SVA constructs while things would be easy if you use functional coverage instead.
Big Advantage to use SVA Coverage model is, Engineer does not required object oriented programming language knowledge :-)
Happy Reading,
ASIC with Ankit
9 comments:
Basically what u are covering is called "scenario coverage". U cant cover address value using SVA. For that u need Fun. coverage.
Basically SVA verifies the scenario or sequence of events to happen as per the specification. If you use cover there means you are covering scenarios.
Dhaval
Hi Dhaval,
Thanks for your such a helpful comments..
As per my understanding there are work arounds through which you can cover things by SVA too. But it would be a huge logic with lots of complexity.
-Ankit
Could you pls share how can we cover address value using SVA and without using bins?
Dhaval
Dhaval,
Actually speaking we can not cover directly like we functional coverge using bins.
But there are ways with which you can make sure that which address has been generated and covered using cover property. This wont be helpfull when we are dealing large address lines.
`define ADDRESS_01 2'b01 (addr == 2'b01)
`define ADDRESS_10 2'b10 (addr == 2'b10)
cov_addr_01 : cover property (@ posedge clk) `ADDRESS_01);
cov_addr_10 : cover property (@ posedge clk) `ADDRESS_10);
Like these you can have cover properties to cover the addresses. This is one way to cover address using property.
Share you views and let me know if I am wrong any where.
Ankit,
Some info is missing.
From asserions you can assign values to vars those are local to assertions only.
In your example you are trying to drive the coverage class's var? If such is the case then you CAN NOT do that.
Dhaval
Generally assertions would be part of module. And define whatever I have defined would be part of module. I am not trying to drive coverage class variable, I am updating define parameters depending on the address values. And the same values I am trying to cover it using cover property.
-ASIC with Ankit
As we know property can be placed inside the class, so we can have a cover property implemendated at transaction level and we can cover transaction related fields there as well.
But the big disadvantage with cover property is you can not have bins, cross coverage, illegal coverage and ignore bins.. which is strong constructs requires for functional coverage.
Share you views and let me know if I am wrong any where.
-ASIC with Anki
U said, "As we know property can be placed inside the class".
Wrong. You can not place property/sequence in class. Read below from SV LRM 2005.
A property can be declared in
— a module
— an interface a program
— a clocking block
— a package
— a compilation-unit scope
Dhaval
Yes Dhaval you are right,
We can not write assertions inside class...!
But still I would say property can be part of program block, we can play with fields of class by taking and object in program block where we will write our property.
-Ankit
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