Dear Readers,
We all know System verilog is becoming hot in verification industry, but still I have seen people who are still arguing on some of the points implemented in System Verilog. The most interesting point which I have come across is "always block is not allowed in program"
To find the reason first thing what I did is, went throug the System Verilog LRM but could not find the reason. LRM has only one line saying that "A program block can contain one or more initial blocks. It cannot contain always blocks, UDPs, modules,interfaces, or other programs." but this statement does not clear the reason and I am not able to find the reason from the LRM.
Then I have started discussion with System Verilog Expert with whom I have been working, I have also went through some of the good websites and some eBooks on System Verilog and found the reason.
Here it is,
SystemVerilog programs are closer to a program in C, with one (or more) entry points, than Verilog’s many small blocks of concurrently executing hardware. In a design, an always block might trigger on every positive edge of a clock from the start of simulation. A testbench, on the other hand, goes through initialization, drive and respond to design activity, and then completes. When the last initial block completes, simulation implicitly ends just as if you had executed $finish. If you had an always block, it would never stop, so you would have to explicitly call $exit to signal that the program block completed.
This is the reason why we can not have always block inside program. Then I am sure you might be thinking on workaround.
So there is a work around, inplace of using always block use "initia forever" to accomplish the same thing.
Happy Informative Reading !!
ASIC With Ankit
We all know System verilog is becoming hot in verification industry, but still I have seen people who are still arguing on some of the points implemented in System Verilog. The most interesting point which I have come across is "always block is not allowed in program"
To find the reason first thing what I did is, went throug the System Verilog LRM but could not find the reason. LRM has only one line saying that "A program block can contain one or more initial blocks. It cannot contain always blocks, UDPs, modules,interfaces, or other programs." but this statement does not clear the reason and I am not able to find the reason from the LRM.
Then I have started discussion with System Verilog Expert with whom I have been working, I have also went through some of the good websites and some eBooks on System Verilog and found the reason.
Here it is,
SystemVerilog programs are closer to a program in C, with one (or more) entry points, than Verilog’s many small blocks of concurrently executing hardware. In a design, an always block might trigger on every positive edge of a clock from the start of simulation. A testbench, on the other hand, goes through initialization, drive and respond to design activity, and then completes. When the last initial block completes, simulation implicitly ends just as if you had executed $finish. If you had an always block, it would never stop, so you would have to explicitly call $exit to signal that the program block completed.
This is the reason why we can not have always block inside program. Then I am sure you might be thinking on workaround.
So there is a work around, inplace of using always block use "initia forever" to accomplish the same thing.
Happy Informative Reading !!
ASIC With Ankit
6 comments:
If I have 3 program blocks in my verification environment (this may be a hypothetical situation), does $exit need to be called explicitly from any of the program block?... Is $exit a system task?
Jay,
$exit is system task and called implicitly when all the "initial" block execution finishes.
For this understanding you dont need to have 3 program blocks, one is enough. Basically program block is starting point of TB. so there can not be 3 program blocks in VE.
Thanks Dhaval for your inputs... I was aware of the most of the facts that you have mentioned. I was just thinking of hypothetical situation, where we have more than one program block. But I am convinced from your reply that in VE, we would never have more than one program block. Thanks a lot for the same.
Thanks Dhaval for your inputs.
I am also convinced, and agree with your response.
-Ankit
Ankit,
I do not agree with your explanation.
If we hook up the thread in program block which runs indefinitely then it behaves like always block.
May be the actual reason lies in question "what is the diff between module and program block?"
Dhaval
Hi Dhaval,
you can break out of a forever loop, So you can terminate the process created by
an initial block. There is no way to terminate the process created by
an always block.
-Ankur
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