Tuesday, October 13, 2009

Who should write Assertion, Designer or Verification Engineer?

Dear Readers,

Who should write Assertion, Designer or Verification Engineer?

The short answer is both. Generally, a designer will write assertions that go in the RTL, while the verification engineer will write assertions that are external to the RTL. For example, designers write assertions that are embedded in the RTL, while the verification engineer writes assertions on the interfaces of the design-under-test (DUT) and creates coverage points, checkers and monitors for the testbench. Verification engineers may also add assertions to fill any holes in the RTL checks left by the designer.

Controlling Assertions:

In any given DUT, there can be many assertions each consisting of one or more evaluation threads. Sometimes it is necessary to enable or disable certain sets of assertions. For example, during reset, all assertions not related to reset must be disabled, and during exception testing, the assertions related to the condition being violated must be disabled.

This means that a fine-grained mechanism must be defined for assertion control. One way to do this is to group assertions logically into categories. One or more categories can then be enabled or disabled at a time.

There are many different mechanisms available for assertion control. Each of the mechanisms has different trade-offs. $asserton/$assertoff system tasks are global mechanisms and can be used to control all assertions or specific named assertions. Compiler directives are compile time directives and allow assertions to be enabled or disabled at compile time. They do not allow assertions to be enabled or disabled dynamically during simulation.

SV has many strong construst and features through which engineer can confident and can say verification is nearly finished. But stil there are many questions comes to my mind are : 1. How do you ensure that there are enough assertions written? 2.How do you say that coverage what is written by you is 100% correct and covering correct behaviour or not?

I am eager to have some inputs on these questions, please share your views.

Happy Reading,
ASIC With Ankit

System Verilog Syntax highlighting for power point

Dear Readers,

Wouldn't it be great if we could colorize the code? would not it be a great if we could save .vim file in to .html with colors?

Many people migh know that we can store our current butter in .vim file with color and save it with the .html extension. If you still dont know how to do that, please do this: Run the following command in a syntax highlighted buffer:

:runtime! syntax/2html.vim

After typing this command, you’ll get a split window with your source in HTML. You can now save it to a file. This command saves the current buffer with a .html extension. Now you can open that extension in your favorite browser and you can copy the colorized text directly into PowerPoint!

Hope this is useful information.

Happy Learning,
ASIC With Ankit