Dear Readers,
In ASIC field, these are the most common questions people use to ask in interviews. So here I would like to share these type of questions with answers that can be useful to brush up fundamentals for ASIC engineer as well as any person who are using languages like Verilog, SystemVerilog, Vera etc...
Que : What is difference between Task and Function in Verilog?
Ans : The following rules distinguish tasks from functions:
Que : How will you generate clock in Verilog?
Ans : There are many ways to generate clock in Verilog we could use one of the following:
Method1:
initial
begin
clk = 0;
end
always begin
#5 clk =~clk ;
end
Method2:
initial
begin
clk = 0;
forever begin
#5 clk =~clk ;
end
end
Method3:
initial
begin
clk = 0;
end
always begin
#5 clk =0;
#5 clk =1;
end
These are the ways which I know, there can be some other ways through which you can generate clock in Verilog. This peace of code can be useful for clock generation where you would like to generate clock.
I will keep updating some more question with answers. Please feel free to shoot me an email if you have any question and suggestions are always welcome. You can drop me an email with your feedback on asicwithankit@gmail.com
Happy Reading,
ASIC With Ankit
In ASIC field, these are the most common questions people use to ask in interviews. So here I would like to share these type of questions with answers that can be useful to brush up fundamentals for ASIC engineer as well as any person who are using languages like Verilog, SystemVerilog, Vera etc...
Que : What is difference between Task and Function in Verilog?
Ans : The following rules distinguish tasks from functions:
- A function shall execute in one simulation time unit;
- A task can contain time-controlling statements.
- A function cannot enable a task;
- A task can enable other tasks or functions.
- A function shall have at least one input type argument and shall not have an output or inout type argument;
- A task can have zero or more arguments of any type.
- A function shall return a single value; a task shall not return a value.
Que : How will you generate clock in Verilog?
Ans : There are many ways to generate clock in Verilog we could use one of the following:
Method1:
initial
begin
clk = 0;
end
always begin
#5 clk =~clk ;
end
Method2:
initial
begin
clk = 0;
forever begin
#5 clk =~clk ;
end
end
Method3:
initial
begin
clk = 0;
end
always begin
#5 clk =0;
#5 clk =1;
end
These are the ways which I know, there can be some other ways through which you can generate clock in Verilog. This peace of code can be useful for clock generation where you would like to generate clock.
I will keep updating some more question with answers. Please feel free to shoot me an email if you have any question and suggestions are always welcome. You can drop me an email with your feedback on asicwithankit@gmail.com
Happy Reading,
ASIC With Ankit
5 comments:
Just a minor change here in syntax:
clk = ~clk; is correct syntax!!!
In method3 first posedge for clock will come after 10 timeunits .. while in method 1 & 2 it comes after 5 timeunits .. Which is wrong .. So method 3 should be lik this:
initial
begin
clk = 0;
end
always begin
#5 clk =1;
#5 clk =0;
end
Hi Jaydip,
These methods gives idea how to generate clock. Clock frequnecy can be user specific, user can decide clock freq as per the application.
As far as I know we can generate clock start from 0 or 1. but only thing is that signal should be toggled inside the always block after specified number of timeunits. Even descripbed method 3 will also generate clock but the only thing is it will generate posedge after 10 timeunits.
Agreed. So as an ASIC verification engineer, which method3 you would prefer?
In my view, regardless of what you code, right from start, clock signal should be toggled at defined regular time interval. which is violated in method3 because first toggling occurs at 10 units while second occurs at 5. Is not it?
Ankit Da,
There is a mistake in answering a question 1. You wrote : "A function shall have at least one input type argument and shall not have an output or inout type argument".
Function is not hard bound to have atleast one input argument.
Dhaval
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