Interview Questions for ASIC

Dear Readers,

Here I would like to post some of the interview question which I have discussed with some senior engineers and industry experts. These are the questions most of the time interviewers asks. Here I will try to explain those all.

Que 1. What is setup and hold time? What will happen if there is setup and hold time violation?
[This question can also asked like "what is metastable state or what is metastability?"]

Ans 1.
Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.

Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

Que 2. What is the difference between latch and flipflop?
[This is the very basic question that most of the interviewer would like to ask to check basic fundamental of digital electronics]

Ans 2.
The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

Que 3. Build a 4:1 mux using 2:1 mux
[This is also a very basic question most interviewer would like to ask]

Ans 3. I would try to explain
Let say we have three 2:1 mux called A'B and C, So here we use two inputs of mux A and two input of mux B (total 4 input, which is the requirement to build 4:1 mux) and output of these two mux (A and B) will be 2 lines which will be input for third mux C. So we will be having 1 output from mux C. Now remaining thing is select line. We will hard wired selection line of A and B and called it as S0 and one select line will be used for mux C called S1. This way we can make a 4:1 mux using 2:1 multiplexer.

Que 4. Implement an AND gate using mux.

Ans 4. For AND gate give one input as select line. Incase if you are using B as a select line connect one input to logic 0 and one input to A.

Oue 5. In pure combinational Ckt, its necessary to mention all the inputs in sensitivity list? Is yes, Why?
Ans 5. Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

Hope this questions and answers are useful for the interested readers.

Happy Reading,
ASIC With Ankit

Basic Interview Questions for ASIC

Dear Readers,

In ASIC field, these are the most common questions people use to ask in interviews. So here I would like to share these type of questions with answers that can be useful to brush up fundamentals for ASIC engineer as well as any person who are using languages like Verilog, SystemVerilog, Vera etc...

Que : What is difference between Task and Function in Verilog?

Ans : The following rules distinguish tasks from functions:

• A function shall execute in one simulation time unit;
• A task can contain time-controlling statements.
• A function cannot enable a task;
• A task can enable other tasks or functions.
• A function shall have at least one input type argument and shall not have an output or inout type argument;
• A task can have zero or more arguments of any type.
• A function shall return a single value; a task shall not return a value.

Que : How will you generate clock in Verilog?
Ans : There are many ways to generate clock in Verilog we could use one of the following:

Method1:
initial
   begin
     clk = 0;
   end
   always begin
     #5 clk =~clk ;
end

Method2:
initial
   begin
      clk = 0;
      forever begin
         #5 clk =~clk ;
      end
   end

Method3:
initial
   begin
      clk = 0;
   end
always begin
   #5 clk =0;
   #5 clk =1;
end

These are the ways which I know, there can be some other ways through which you can generate clock in Verilog. This peace of code can be useful for clock generation where you would like to generate clock.

I will keep updating some more question with answers. Please feel free to shoot me an email if you have any question and suggestions are always welcome. You can drop me an email with your feedback on asicwithankit@gmail.com

Happy Reading,
ASIC With Ankit