Wednesday, February 27, 2013

System Verilog : Final means Final !

Dear Readers,

Today I would like to share some basic things on ‘final’ block in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summary information. You can have summary information printed in log file at the end of simulation.

Final block executes at the end of the simulations without delays. ‘final’ block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to ‘function’.Function also executes in zero time and does not allow timing related or blocking type of activities.

Lets try to understand this with syntax:

program asic_with_ankit;
   int error, warning;

    initial begin

      //Main program activities…..
    end
 
   final begin
      $display (“Test is done with %d errors and %d warnings”, error, warning);
    end
endprogram

Simulation ends means what?

Simulation ends when last initial block ends in the program. When last initial block ends, it implicitly calls $exit which tells particular program is done! When every program is completed (exited) an implicit call to $finish is done. User can call $finish any time whenever he/she wants to end the simulation.

This process does not mean that your simulation is over, a module or program can have one or more ‘final’blocks that contains code to be run just before simulator terminates/finishes.

This is a great place to perform certain activity in your simulation like:
  • Cleaning up tasks such as closing files
  • Printing reports which can have summary of number of warnings, errors etc..
  • Display statistic information about the simulation
final block can only trigger once in a simulations and because of this I name it as ‘final means final! :) you cannot call it again!

Happy Reading,
ASIC With Ankit

Thursday, February 14, 2013

Is Test bench complex and difficult to handle at end of the day?

Dear Readers,

As we all know debugging is not an easy task and requires lots of attentions and effort to figure out the issues! Well, it is not at free of cost! (Debugging is not free!) This is true for both Design as well as Verification engineers.

ASIC/FPGAs are becoming more and more complex day by day and because of that RTL design and Verification environments are becoming super complex! Usually engineers start writing a code with good understanding in mind from defined specification or standards. With the complexity and sometime way of writing code makes design code / verification environment complex and difficult to handle. When debugging comes in picture, sometime discussion makes debugging easy. Thinking of possible scenarios, causes and problem solving ideas varies engineers to engineers! When you stuck with debugging some issue and you don’t get any clue, don’t spend huge amount of time debugging the same issue because “debugging is not free”, instead try discussing the scenario with your team mates, you would mostly get the hint or clue to identify and fix the issues. Obviously your colleague should be supportive in nature :). This is one of the potential places where TEAM work comes in picture!

Why the verification or design code becomes complex to handle at end of the day? What could be potential reason for this?
  1. Written code for Design/Verification itself is complex (because of thousands of functionalities, sometime because of way of writing)
  2. Engineers who have developed the design/verification environment start from scratch and leave the organization (Potential reason for now a day). In this case engineers leave with their all learning, concepts, tricks, algorithms and actual flow!
  3. When you don’t prepare architecture specification (top level as well as micro level). In this case you have to always rely on people who have been working on from years! This creates a solid dependencies for company, if those person leave because of any reason, it becomes very tough to maintain the design and verification environment for somebody who is new.
Customers always in hurry and wants their product ready and bug free! Critical situation comes when customer comes with their problem or with some new requirement support in design and you don’t have experienced person who have worked on this product. In this case engineers might face sleepless nights and will have to put lots and lots of efforts (because, they are not well aware of the design) to fulfill the requirement. Same requirements would have been fulfill with less amount of effort and as per expectation from client if engineers who have worked on this product are working!!
How could we avoid this type of pains?
  1. By making a habit of writing architectural documents with details. There could be different types of documents like top level architectural spec (which is useful for presentation), Micro level architectural documents (useful for engineers who are currently working and who will work in future as reference). Same is applicable for verification engineers for the architecture of verification environments.
  2. By not creating dependencies at certain level on any engineers and making sure that engineers keeps documenting changes/implementation done by them.
  3. By scheduling presentation/discussion on architecture and flow understanding for TEAM so that engineers working on the same product/protocol will gets understanding on flow.
  4. By following the standard verification methodology to reduce the pain of handing environment at certain extend since most of the methodology are user friendly and have many controls to handle complex environments.
Same blog post has been published on EDACafe blog portal, to access the same click here.
Happy Reading,

ASIC-FPGA Design Verification: Running Short of Business or Resource?

Dear Readers,

As we all know the semiconductor market looks good now days and lots of companies are hiring talents for 2013-14 projection. If we keep this projection in mind, we could say there would be a business for the companies for upcoming years. Now, the billion dollar question: ‘how about the resources’?

We have been observing from last few months that companies are struggling in finding good experienced/skilled resources. Usually product/service companies are playing with smart approach of having hierarchical engineering model where there are few junior/college graduates engineers working under guidance of one senior/Lead engineer. Approach looks smart and efficient to utilize resources appropriately and makes engineering execution cost effective too! At the same time executive and managers always thinks on cost effective and efficient engineering model to fulfill dynamic time to market! Many companies are working with different approach to utilize and manage engineering resources efficiently.

There are cases or project specific critical requirements where you don’t have time to train your junior resources, in this type of requirement; you cannot take a chance of using junior level resource, if you do so, you might lose the schedule, budget and at the end market which is very important! There could be a requirement where you don’t need all your skilled resources to work on. For this type of requirement you can create a hierarchical approach of your engineering model to use the skillset efficiently. (This is where the engineering management comes in picture, Managers; Executives have to take efficient decisions to move forward in this type of situation otherwise in long go, you could see impact on quality and customer)

Now a day, most requirements and needs from the product based companies are for senior engineers, considering the critical project requirement and quick execution to make the products ahead in the market. Companies are feeling shortage of skilled resources. At the same time people don’t move easily! Question here is; Does this create shortage of experienced skillsets?

When market is in good shape, revenue and financial graph is growing mostly all the companies are in need of skilled man power and that’s where competition comes in picture for companies and engineers too! There can be different type of situations where market is not in good shape and companies are struggling to get the business. In these types of situation Smart companies usually starts investing in engineering man power to develop the skillsets keeping projection in mind, by the time skilled requirement comes, company already have skilled/trained resources ready to jump in to!

There can be other type of situation where market might or might not be in good shape. Irrespective of market Situations Company sometime announces on ‘restructuring the engineering force’ which means company directly or indirectly fires engineers as a part re-structuring. Mostly this situation comes because of shortage of business for company (particular business division of company).

These types of situations are still debatable and require dynamic changes based on the market, need, requirements etc… But still the question remains same at any point of time ‘Are Companies Running Short Of Business or Short Of Resource?

Same blog post has been published on EETimes blog portal:

You can read same blog post on EETIndia, click here !

Thanks,
ASIC With Ankit