Tuesday, March 27, 2012

Polymorphism: One of the most important feature for Test Bench Development.

Dear Readers,

Here I would like to share basic and most important fundamental of OOP (Object Oriented Programing) language 'polymorphism'. Polymorphism is one of the most important feature used in Test Bench development using System Verilog. Understanding of this fundamental is very important if you are planing to work with System Verilog with any kind of methodology (AVM, VMM, OVM, UVM).

Definition of Polymorphism :
As per the SV LRM "Polymorphism allows the use of the variable in the superclass to hold sublcass object and to reference the methods of those subclasses directly from the superclass variable."
 Which means, A single task can be implemented using the same name and implemented differently as each type in object hierarchy requires. Later when polymorpic object (whose type is not known at compile time) executes the virtual method and the correct implementation is chosen and executed at run time.

To achieve polymorphism the 'virtual' identifier must be used when defining the base class and method(s) within that class.

Let me give you a brief example to understand polymorphism in detail which helps you in your test bench development:


Note: Click on the image to see example with big fonts

When you run above example you will see below result:

Output :
send Method from class 'Base'
send method from class 'Ext_Base'

You will see in example line number 30 where Extended class from base class 'ext_b' has been allocated a memory by doing new and then on line number 31 we assigned a memory between two objects (b and ext_b). Now when we called b.send(), it will call extended class method. This is called polymorphism.

Hope this example, with explanation gives you a better idea on polymorphism. I am sure this will helps you in your test bench development.

Enjoy !
ASIC With Ankit